End of file fix

docs/source/using_yosys/more_scripting/data_flow_tracking.rst

@@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other
 input is either 1 or carries a tag of the same group. So if one input is ``0,
 "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a",
 "key:b"``, rather than simply ``0``. Note that if we add an unrelated
-``"overflow"`` tag to the first input, it would still not be propagated.
+``"overflow"`` tag to the first input, it would still not be propagated.

docs/source/using_yosys/synthesis/abc.rst

@@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
 critical path, while the generally-longer paths result in ABC9 being able to
 reduce design area by mapping other logic to slower cells with greater logic
 density.
-

docs/source/using_yosys/synthesis/extract.rst

@@ -228,4 +228,4 @@ Unwrap in ``test2``:
     :end-before: end part e
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
-    :class: width-helper invert-helper
+    :class: width-helper invert-helper

docs/source/using_yosys/synthesis/index.rst

@@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
    extract
    abc
    cell_libs
-

docs/source/using_yosys/synthesis/memory.rst

@@ -787,4 +787,3 @@ Asynchronous writes
 	end
 
 	assign read_data = mem[read_addr];
-