End of file fix

docs/source/appendix/env_vars.rst

@@ -29,4 +29,3 @@ Yosys environment variables
 ``YOSYS_ABORT_ON_LOG_ERROR``
    Can be used for debugging Yosys internals.  Setting it to 1 causes abort() to
    be called when Yosys terminates with an error message.
-

docs/source/cell/word_logic.rst

@@ -43,4 +43,4 @@ values.
 .. autocellgroup:: logic
    :members:
    :source:
-   :linenos:
+   :linenos:

docs/source/code_examples/intro/mycells.v

@@ -20,4 +20,3 @@ output reg Q;
 always @(posedge C)
 	Q <= D;
 endmodule
-

docs/source/code_examples/macc/Makefile

@@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2
 
 design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format dot -notitle
-

docs/source/code_examples/macro_commands/synth_ice40.ys

@@ -88,4 +88,4 @@ check:
     stat
     check -noinit
     blackbox =A:whitebox
-        
+        

docs/source/code_examples/opt/opt_merge.ys

@@ -15,4 +15,3 @@ opt_merge after
 clean
 
 show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/opt/opt_muxtree.ys

@@ -14,4 +14,3 @@ opt_muxtree after
 clean
 
 show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/scrambler/scrambler.ys

@@ -19,4 +19,3 @@ eval -set in 1 -show out
 eval -set in 270369 -show out
 
 sat -set out 632435482
-

docs/source/code_examples/synth_flow/Makefile

@@ -17,4 +17,3 @@ examples:
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/using_yosys/more_scripting/data_flow_tracking.rst

@@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other
 input is either 1 or carries a tag of the same group. So if one input is ``0,
 "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a",
 "key:b"``, rather than simply ``0``. Note that if we add an unrelated
-``"overflow"`` tag to the first input, it would still not be propagated.
+``"overflow"`` tag to the first input, it would still not be propagated.

docs/source/using_yosys/synthesis/abc.rst

@@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
 critical path, while the generally-longer paths result in ABC9 being able to
 reduce design area by mapping other logic to slower cells with greater logic
 density.
-

docs/source/using_yosys/synthesis/extract.rst

@@ -228,4 +228,4 @@ Unwrap in ``test2``:
     :end-before: end part e
 
 .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
-    :class: width-helper invert-helper
+    :class: width-helper invert-helper

docs/source/using_yosys/synthesis/index.rst

@@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
    extract
    abc
    cell_libs
-

docs/source/using_yosys/synthesis/memory.rst

@@ -787,4 +787,3 @@ Asynchronous writes
 	end
 
 	assign read_data = mem[read_addr];
-

docs/source/yosys_internals/extending_yosys/index.rst

@@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds.
    advanced_bugpoint
    contributing
    test_suites
-

docs/source/yosys_internals/extending_yosys/test_suites.rst

@@ -194,4 +194,3 @@ compiler versions.  For up to date information, including OS versions, refer to
    .. code-block:: console
 
       cmake --build build --target test-unit
-

docs/source/yosys_internals/flow/index.rst

@@ -16,4 +16,3 @@ These scripts contain three types of commands:
 	overview
 	control_and_data
 	verilog_frontend
-

docs/source/yosys_internals/formats/index.rst

@@ -56,4 +56,3 @@ constructs must be called from the synthesis script first.
 .. [1]
    In Yosys the term pass is only used to refer to commands that operate on the
    RTLIL data structure.
-