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Liberty file parser now accepts superfluous ;

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This commit is contained in:
Niels Moseley 2019-03-27 15:15:53 +01:00
parent 7682629b79
commit 487cb45b87
4 changed files with 151 additions and 9 deletions
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3
tests/liberty/normal.lib
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@ -142,8 +142,7 @@ library(supergate) {
}
/* D-type flip-flop with asynchronous reset and preset */
cell (dff)
{
cell (dff) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";

48
tests/liberty/processdefs.lib Normal file
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@ -0,0 +1,48 @@
/********************************************/
/* */
/* Supergate cell library for Bench marking */
/* */
/* Symbiotic EDA GmbH / Moseley Instruments */
/* Niels A. Moseley */
/* */
/* Process: none */
/* */
/* Date : 25-03-2019 */
/* Version: 1.0 */
/* */
/********************************************/
library(processdefs) {
technology (cmos);
revision : 1.0;
time_unit : "1ps";
pulling_resistance_unit : "1kohm";
voltage_unit : "1V";
current_unit : "1uA";
capacitive_load_unit(1,ff);
default_inout_pin_cap : 7.0;
default_input_pin_cap : 7.0;
default_output_pin_cap : 0.0;
default_fanout_load : 1.0;
default_wire_load_capacitance : 0.1;
default_wire_load_resistance : 1.0e-3;
default_wire_load_area : 0.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.2;
delay_model : generic_cmos;
define_cell_area(bond_pads,pad_slots)
input_voltage(cmos) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
}

48
tests/liberty/semicolextra.lib Normal file
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@ -0,0 +1,48 @@
/*
Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
fall_constraint (SETUP_HOLD) formatting.
*/
library(supergate) {
technology (cmos);
revision : 1.0;
cell (DFF) {
cell_footprint : dff;
area : 50;
pin(D) {
direction : input;
capacitance : 0.002;
timing() {
related_pin : "CK";
timing_type : setup_rising;
fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
"0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
"0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
"0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
"1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
}
}
pin(CK) {
direction : input;
clock : true;
capacitance : 0.00290;
}
ff(IQ,IQN) {
clocked_on : "CK";
next_state : "D";
}
pin(Q) {
direction : output;
capacitance : 0.003;
max_capacitance : 0.3;
}
cell_leakage_power : 0.3;
}
}