mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Split latches into separete tests

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-04 09:24:22 +02:00
parent fba6229718
commit 487b38b124
2 changed files with 27 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

34
tests/xilinx/latches.v
View file

@ -22,37 +22,3 @@ module latchsr
else if ( en ) else if ( en )
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2
);
latchp u_latchp (
.en (clk ),
.d (a ),
.q (b )
);
latchn u_latchn (
.en (clk ),
.d (a ),
.q (b1 )
);
latchsr u_latchsr (
.en (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b2 )
);
endmodule

35
tests/xilinx/latches.ys
View file

@ -2,15 +2,34 @@ read_verilog latches.v
design -save read design -save read
proc proc
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock hierarchy -top latchp
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
synth_xilinx select -assert-none t:LDCE %% t:* %D
flatten
cd top
design -load read
proc
hierarchy -top latchn
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 1 t:LUT1 select -assert-count 1 t:LUT1
select -assert-none t:LDCE t:LUT1 %% t:* %D
design -load read
proc
hierarchy -top latchsr
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 2 t:LUT3 select -assert-count 2 t:LUT3
#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
select -assert-count 3 t:$_DLATCH_P_ select -assert-none t:LDCE t:LUT3 %% t:* %D
select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D