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Fixes needed for DFF circuits

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This commit is contained in:
Eddie Hung 2019-02-15 15:22:18 -08:00
parent a786ac4d53
commit 486a270415
1 changed files with 3 additions and 4 deletions
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5
backends/aiger/xaiger.cc
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@ -137,7 +137,7 @@ struct XAigerWriter
if (bit.wire == nullptr) { if (bit.wire == nullptr) {
if (wire->port_output) { if (wire->port_output) {
aig_map[wirebit] = (bit == State::S1) ? 1 : 0; aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
output_bits.insert(wirebit); //output_bits.insert(wirebit);
} }
continue; continue;
} }
@ -220,7 +220,6 @@ struct XAigerWriter
} }
else if (cell->output(c.first)) { else if (cell->output(c.first)) {
SigBit O = sigmap(b); SigBit O = sigmap(b);
if (!w->port_output)
ci_bits.insert(O); ci_bits.insert(O);
undriven_bits.erase(O); undriven_bits.erase(O);
} }
@ -525,7 +524,7 @@ struct XAigerWriter
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
} }
if (wire->port_output || co_bits.count(RTLIL::SigBit{wire, i})) { if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) {
int o = ordered_outputs.at(sig[i]); int o = ordered_outputs.at(sig[i]);
output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
} }