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abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)

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This commit is contained in:
Eddie Hung 2020-01-14 16:33:41 -08:00
parent 48984a7605
commit 485e08e436
2 changed files with 3 additions and 3 deletions
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2
backends/aiger/xaiger.cc
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@ -318,7 +318,7 @@ struct XAigerWriter
RTLIL::Module* box_module = module->design->module(cell->type); RTLIL::Module* box_module = module->design->module(cell->type);
log_assert(box_module); log_assert(box_module);
log_assert(box_module->attributes.count("\\abc9_box_id")); log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
auto r = box_ports.insert(cell->type); auto r = box_ports.insert(cell->type);
if (r.second) { if (r.second) {

4
passes/techmap/abc9_ops.cc
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@ -117,7 +117,7 @@ void check(RTLIL::Design *design)
if (wire->port_output) num_outputs++; if (wire->port_output) num_outputs++;
} }
if (num_outputs != 1) if (num_outputs != 1)
log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs); log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
} }
} }
} }
@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(cell); log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type); RTLIL::Module* box_module = design->module(cell->type);
if (!box_module || !box_module->attributes.count("\\abc9_box_id")) if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
continue; continue;
cell->attributes["\\abc9_box_seq"] = box_count++; cell->attributes["\\abc9_box_seq"] = box_count++;