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	RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.
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					 2 changed files with 12 additions and 2 deletions
				
			
		|  | @ -1536,13 +1536,13 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const | |||
| 		new_mod->addWire(it.first, it.second); | ||||
| 
 | ||||
| 	for (auto &it : memories) | ||||
| 		new_mod->memories[it.first] = new RTLIL::Memory(*it.second); | ||||
| 		new_mod->addMemory(it.first, it.second); | ||||
| 
 | ||||
| 	for (auto &it : cells_) | ||||
| 		new_mod->addCell(it.first, it.second); | ||||
| 
 | ||||
| 	for (auto &it : processes) | ||||
| 		new_mod->processes[it.first] = it.second->clone(); | ||||
| 		new_mod->addProcess(it.first, it.second); | ||||
| 
 | ||||
| 	struct RewriteSigSpecWorker | ||||
| 	{ | ||||
|  | @ -1913,6 +1913,14 @@ RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memor | |||
| 	return mem; | ||||
| } | ||||
| 
 | ||||
| RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other) | ||||
| { | ||||
| 	RTLIL::Process *proc = other->clone(); | ||||
| 	proc->name = name; | ||||
| 	processes[name] = proc; | ||||
| 	return proc; | ||||
| } | ||||
| 
 | ||||
| #define DEF_METHOD(_func, _y_size, _type) \ | ||||
| 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ | ||||
| 		RTLIL::Cell *cell = addCell(name, _type);           \ | ||||
|  |  | |||
|  | @ -1175,6 +1175,8 @@ public: | |||
| 
 | ||||
| 	RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); | ||||
| 
 | ||||
| 	RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other); | ||||
| 
 | ||||
| 	// The add* methods create a cell and return the created cell. All signals must exist in advance.
 | ||||
| 
 | ||||
| 	RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); | ||||
|  |  | |||
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