mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 22:23:23 +00:00
Code Activity

Added read_verilog -sv options, added support for bit, logic,

Browse source 
allways_ff, always_comb, and always_latch
This commit is contained in:
Clifford Wolf 2014-06-12 11:54:20 +02:00
parent 9a6cd64fc2
commit 482d9208aa
7 changed files with 52 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

3
frontends/verilog/verilog_frontend.h
View file

@ -45,6 +45,9 @@ namespace VERILOG_FRONTEND
// state of `default_nettype
extern bool default_nettype_wire;
// running in SystemVerilog mode
extern bool sv_mode;
}
// the pre-processor