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Added read_verilog -sv options, added support for bit, logic,

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allways_ff, always_comb, and always_latch
This commit is contained in:
Clifford Wolf 2014-06-12 11:54:20 +02:00
parent 9a6cd64fc2
commit 482d9208aa
7 changed files with 52 additions and 8 deletions
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17
frontends/verilog/lexer.l
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@ -52,6 +52,14 @@ namespace VERILOG_FRONTEND {
std::vector<int> ln_stack;
}
#define SV_KEYWORD(_tok) \
if (sv_mode) return _tok; \
log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
"recognized unless read_verilog is called with -sv!\n", yytext, \
AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
%}
%option yylineno
@ -143,7 +151,14 @@ namespace VERILOG_FRONTEND {
"while" { return TOK_WHILE; }
"repeat" { return TOK_REPEAT; }
"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }
"always_comb" { SV_KEYWORD(TOK_ALWAYS); }
"always_ff" { SV_KEYWORD(TOK_ALWAYS); }
"always_latch" { SV_KEYWORD(TOK_ALWAYS); }
"assert" { SV_KEYWORD(TOK_ASSERT); }
"property" { SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }