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Indirection via $__soft_mul

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This commit is contained in:
Eddie Hung 2019-07-19 20:20:33 -07:00
parent 595a8f032f
commit 47fd042b9f
2 changed files with 10 additions and 9 deletions
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18
techlibs/common/mul2dsp.v
View file

@ -28,9 +28,7 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
if (A_SIGNED != B_SIGNED) if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
wire _TECHMAP_FAIL_ = 1;
else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED == 0 from here // NB: A_SIGNED == B_SIGNED == 0 from here
else if (A_WIDTH >= B_WIDTH) else if (A_WIDTH >= B_WIDTH)
@ -212,7 +210,7 @@ module \$__mul (A, B, Y);
endmodule endmodule
(* techmap_celltype = "$__mul" *) (* techmap_celltype = "$__mul" *)
module _90_internal_mul_to_external (A, B, Y); module $__soft_mul (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
@ -223,9 +221,11 @@ module _90_internal_mul_to_external (A, B, Y);
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
// Indirection necessary since mapping
// back to $mul will cause recursion
generate generate
if (A_SIGNED && !B_SIGNED) if (A_SIGNED && !B_SIGNED)
\$mul #( \$__soft__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
@ -233,23 +233,23 @@ module _90_internal_mul_to_external (A, B, Y);
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(A),
.B({1'b0, B}), .B({1'b0,B}),
.Y(Y) .Y(Y)
); );
else if (!A_SIGNED && B_SIGNED) else if (!A_SIGNED && B_SIGNED)
\$mul #( \$__soft_mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH+1), .A_WIDTH(A_WIDTH+1),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A({1'b0, A}), .A({1'b0,A}),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
else else
\$mul #( \$__soft_mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),

1
techlibs/ice40/synth_ice40.cc
View file

@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass
if (help_mode || dsp) { if (help_mode || dsp) {
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
run("ice40_dsp", "(if -dsp)"); run("ice40_dsp", "(if -dsp)");
run("chtype -set $mul t:$__soft_mul");
} }
run("alumacc"); run("alumacc");
run("opt"); run("opt");