diff --git a/kernel/ffinit.h b/kernel/ffinit.h
index 6d4c97ac3..66c13b68f 100644
--- a/kernel/ffinit.h
+++ b/kernel/ffinit.h
@@ -27,10 +27,10 @@ YOSYS_NAMESPACE_BEGIN
 
 struct FfInitVals
 {
-	const SigMap *sigmap;
+	const SigMapView *sigmap;
 	dict<SigBit, std::pair<State,SigBit>> initbits;
 
-	void set(const SigMap *sigmap_, RTLIL::Module *module)
+	void set(const SigMapView *sigmap_, RTLIL::Module *module)
 	{
 		sigmap = sigmap_;
 		initbits.clear();
@@ -126,7 +126,7 @@ struct FfInitVals
 		initbits.clear();
 	}
 
-	FfInitVals (const SigMap *sigmap, RTLIL::Module *module)
+	FfInitVals (const SigMapView *sigmap, RTLIL::Module *module)
 	{
 		set(sigmap, module);
 	}
diff --git a/kernel/ffmerge.h b/kernel/ffmerge.h
index 5428da324..028987503 100644
--- a/kernel/ffmerge.h
+++ b/kernel/ffmerge.h
@@ -58,7 +58,7 @@ YOSYS_NAMESPACE_BEGIN
 
 struct FfMergeHelper
 {
-	const SigMap *sigmap;
+	const SigMapView *sigmap;
 	RTLIL::Module *module;
 	FfInitVals *initvals;
 
diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index 4144d701d..fdde7696d 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -1327,7 +1327,8 @@ public:
 		return p;
 	}
 
-	// Merge sets if the given indices belong to different sets
+	// Merge sets if the given indices belong to different sets.
+	// Makes ifind(j) the root of the merged set.
 	void imerge(int i, int j)
 	{
 		i = ifind(i);
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 3b0d7b40d..7962eaa70 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -237,6 +237,42 @@ using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell
 template<typename T>
 class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
 
+struct SigMapView
+{
+	mfp<SigBit> database;
+
+	// Modify bit to its representative
+	void apply(RTLIL::SigBit &bit) const
+	{
+		bit = database.find(bit);
+	}
+
+	void apply(RTLIL::SigSpec &sig) const
+	{
+		for (auto &bit : sig)
+			apply(bit);
+	}
+
+	RTLIL::SigBit operator()(RTLIL::SigBit bit) const
+	{
+		apply(bit);
+		return bit;
+	}
+
+	RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
+	{
+		apply(sig);
+		return sig;
+	}
+
+	RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
+	{
+		SigSpec sig(wire);
+		apply(sig);
+		return sig;
+	}
+};
+
 /**
  * SigMap wraps a union-find "database"
  * to map SigBits of a module to canonical representative SigBits.
@@ -244,10 +280,8 @@ class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name
  * If a SigBit has a const state (impl: bit.wire is nullptr),
  * it's promoted to a representative.
  */
-struct SigMap
+struct SigMap final : public SigMapView
 {
-	mfp<SigBit> database;
-
 	SigMap(RTLIL::Module *module = NULL)
 	{
 		if (module != NULL)
@@ -320,37 +354,6 @@ struct SigMap
 
 	inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }
 
-	// Modify bit to its representative
-	void apply(RTLIL::SigBit &bit) const
-	{
-		bit = database.find(bit);
-	}
-
-	void apply(RTLIL::SigSpec &sig) const
-	{
-		for (auto &bit : sig)
-			apply(bit);
-	}
-
-	RTLIL::SigBit operator()(RTLIL::SigBit bit) const
-	{
-		apply(bit);
-		return bit;
-	}
-
-	RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
-	{
-		apply(sig);
-		return sig;
-	}
-
-	RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
-	{
-		SigSpec sig(wire);
-		apply(sig);
-		return sig;
-	}
-
 	// All non-const bits
 	RTLIL::SigSpec allbits() const
 	{
@@ -362,6 +365,107 @@ struct SigMap
 	}
 };
 
+/**
+ * SiValgMap wraps a union-find "database" to map SigBits of a module to
+ * canonical representative SigBits plus some optional Val value associated with the bits.
+ * Val has a commutative, associative, idempotent operator|=, a default constructor
+ * which constructs an identity element, and a copy constructor.
+ * SigBits that are connected share a set in the underlying database;
+ * the associated value is the "sum" of all the values associated with the contributing bits.
+ * If any of the SigBits in a set are a constant, the canonical SigBit is a constant.
+ */
+template <class Val>
+struct SigValMap final : public SigMapView
+{
+	dict<SigBit, Val> values;
+
+	void swap(SigValMap<Val> &other)
+	{
+		database.swap(other.database);
+		values.swap(other.values);
+	}
+
+	void clear()
+	{
+		database.clear();
+		values.clear();
+	}
+
+	// Rebuild SigMap for all connections in module
+	void set(RTLIL::Module *module)
+	{
+		int bitcount = 0;
+		for (auto &it : module->connections())
+			bitcount += it.first.size();
+
+		database.clear();
+		values.clear();
+		database.reserve(bitcount);
+
+		for (auto &it : module->connections())
+			add(it.first, it.second);
+	}
+
+	// Add connections from "from" to "to", bit-by-bit.
+	void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
+	{
+		log_assert(GetSize(from) == GetSize(to));
+
+		for (int i = 0; i < GetSize(from); i++)
+		{
+			int bfi = database.lookup(from[i]);
+			int bti = database.lookup(to[i]);
+			if (bfi == bti) {
+				continue;
+			}
+
+			const RTLIL::SigBit &bf = database[bfi];
+			const RTLIL::SigBit &bt = database[bti];
+			if (bf.wire == nullptr) {
+				// bf is constant so make it the canonical representative.
+				database.imerge(bti, bfi);
+				merge_value(bt, bf);
+			} else {
+				// Make bt the canonical representative.
+				database.imerge(bfi, bti);
+				merge_value(bf, bt);
+			}
+		}
+	}
+
+	void addVal(const RTLIL::SigBit &bit, const Val &val)
+	{
+		values[database.find(bit)] |= val;
+	}
+
+	void addVal(const RTLIL::SigSpec &sig, const Val &val)
+	{
+		for (const auto &bit : sig)
+			addVal(bit, val);
+	}
+
+	Val apply_and_get_value(RTLIL::SigBit &bit) const
+	{
+		bit = database.find(bit);
+		auto it = values.find(bit);
+		return it == values.end() ? Val() : it->second;
+	}
+
+private:
+	void merge_value(const RTLIL::SigBit &from, const RTLIL::SigBit &to)
+	{
+		auto it = values.find(from);
+		if (it == values.end()) {
+			return;
+		}
+		// values[to] could resize the underlying `entries` so
+		// finish using `it` first.
+		Val v = it->second;
+		values.erase(it);
+		values[to] |= v;
+	}
+};
+
 YOSYS_NAMESPACE_END
 
 #endif /* SIGTOOLS_H */
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index cc37677ce..e79566d3b 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -113,25 +113,81 @@ bool map_mux8;
 bool map_mux16;
 
 bool markgroups;
-int map_autoidx;
-SigMap assign_map;
-RTLIL::Module *module;
-std::vector<gate_t> signal_list;
-dict<RTLIL::SigBit, int> signal_map;
-FfInitVals initvals;
+
 pool<std::string> enabled_gates;
 bool cmos_cost;
-bool had_init;
 
-bool clk_polarity, en_polarity, arst_polarity, srst_polarity;
-RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
-dict<int, std::string> pi_map, po_map;
-
-int undef_bits_lost;
-
-int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
+struct AbcConfig
 {
-	assign_map.apply(bit);
+	std::string script_file;
+	std::string exe_file;
+	std::vector<std::string> liberty_files;
+	std::vector<std::string> genlib_files;
+	std::string constr_file;
+	vector<int> lut_costs;
+	std::string delay_target;
+	std::string sop_inputs;
+	std::string sop_products;
+	std::string lutin_shared;
+	std::vector<std::string> dont_use_cells;
+	bool cleanup = true;
+	bool keepff = false;
+	bool fast_mode = false;
+	bool show_tempdir = false;
+	bool sop_mode = false;
+	bool abc_dress = false;
+};
+
+struct AbcSigVal {
+	bool is_port;
+
+	AbcSigVal(bool is_port = false) : is_port(is_port) {}
+	AbcSigVal &operator|=(const AbcSigVal &other) {
+		is_port |= other.is_port;
+		return *this;
+	}
+};
+
+using AbcSigMap = SigValMap<AbcSigVal>;
+
+struct AbcModuleState {
+	const AbcConfig &config;
+
+	int map_autoidx = 0;
+	std::vector<gate_t> signal_list;
+	dict<RTLIL::SigBit, int> signal_map;
+	FfInitVals initvals;
+	bool had_init = false;
+	bool did_run_abc = false;
+
+	bool clk_polarity = false;
+	bool en_polarity = false;
+	bool arst_polarity = false;
+	bool srst_polarity = false;
+	RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
+	dict<int, std::string> pi_map, po_map;
+
+	int undef_bits_lost = 0;
+
+	std::string tempdir_name;
+
+	AbcModuleState(const AbcConfig &config) : config(config) {}
+
+	int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
+	void mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig);
+	bool extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff);
+	std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr);
+	void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts);
+	void handle_loops(AbcSigMap &assign_map, RTLIL::Module *module);
+	void abc_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector<RTLIL::Cell*> &cells,
+		bool dff_mode, std::string clk_str);
+	void extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module);
+	void finish();
+};
+
+int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type, int in1, int in2, int in3, int in4)
+{
+	AbcSigVal val = assign_map.apply_and_get_value(bit);
 
 	if (bit == State::Sx)
 		undef_bits_lost++;
@@ -144,7 +200,7 @@ int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1,
 		gate.in2 = -1;
 		gate.in3 = -1;
 		gate.in4 = -1;
-		gate.is_port = false;
+		gate.is_port = bit.wire != nullptr && val.is_port;
 		gate.bit = bit;
 		gate.init = initvals(bit);
 		signal_list.push_back(gate);
@@ -167,40 +223,40 @@ int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1,
 	return gate.id;
 }
 
-void mark_port(RTLIL::SigSpec sig)
+void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
 {
 	for (auto &bit : assign_map(sig))
 		if (bit.wire != nullptr && signal_map.count(bit) > 0)
 			signal_list[signal_map[bit]].is_port = true;
 }
 
-void extract_cell(RTLIL::Cell *cell, bool keepff)
+bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
 {
 	if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
 		FfData ff(&initvals, cell);
 		gate_type_t type = G(FF);
 		if (!ff.has_clk)
-			return;
+			return false;
 		if (ff.has_gclk)
-			return;
+			return false;
 		if (ff.has_aload)
-			return;
+			return false;
 		if (ff.has_sr)
-			return;
+			return false;
 		if (!ff.is_fine)
-			return;
+			return false;
 		if (clk_polarity != ff.pol_clk)
-			return;
+			return false;
 		if (clk_sig != assign_map(ff.sig_clk))
-			return;
+			return false;
 		if (ff.has_ce) {
 			if (en_polarity != ff.pol_ce)
-				return;
+				return false;
 			if (en_sig != assign_map(ff.sig_ce))
-				return;
+				return false;
 		} else {
 			if (GetSize(en_sig) != 0)
-				return;
+				return false;
 		}
 		if (ff.val_init == State::S1) {
 			type = G(FF1);
@@ -211,50 +267,53 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		}
 		if (ff.has_arst) {
 			if (arst_polarity != ff.pol_arst)
-				return;
+				return false;
 			if (arst_sig != assign_map(ff.sig_arst))
-				return;
+				return false;
 			if (ff.val_arst == State::S1) {
 				if (type == G(FF0))
-					return;
+					return false;
 				type = G(FF1);
 			} else if (ff.val_arst == State::S0) {
 				if (type == G(FF1))
-					return;
+					return false;
 				type = G(FF0);
 			}
 		} else {
 			if (GetSize(arst_sig) != 0)
-				return;
+				return false;
 		}
 		if (ff.has_srst) {
 			if (srst_polarity != ff.pol_srst)
-				return;
+				return false;
 			if (srst_sig != assign_map(ff.sig_srst))
-				return;
+				return false;
 			if (ff.val_srst == State::S1) {
 				if (type == G(FF0))
-					return;
+					return false;
 				type = G(FF1);
 			} else if (ff.val_srst == State::S0) {
 				if (type == G(FF1))
-					return;
+					return false;
 				type = G(FF0);
 			}
 		} else {
 			if (GetSize(srst_sig) != 0)
-				return;
+				return false;
 		}
 
-		if (keepff)
-			for (auto &c : ff.sig_q.chunks())
-				if (c.wire != nullptr)
-					c.wire->attributes[ID::keep] = 1;
+		int gate_id = map_signal(assign_map, ff.sig_q, type, map_signal(assign_map, ff.sig_d));
+		if (keepff) {
+			SigBit bit = ff.sig_q;
+			if (assign_map(bit).wire != nullptr) {
+				signal_list[gate_id].is_port = true;
+			}
+		}
 
-		map_signal(ff.sig_q, type, map_signal(ff.sig_d));
+		map_signal(assign_map, ff.sig_q, type, map_signal(assign_map, ff.sig_d));
 
 		ff.remove();
-		return;
+		return true;
 	}
 
 	if (cell->type.in(ID($_BUF_), ID($_NOT_)))
@@ -265,10 +324,10 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_y);
 
-		map_signal(sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(sig_a));
+		map_signal(assign_map, sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(assign_map, sig_a));
 
 		module->remove(cell);
-		return;
+		return true;
 	}
 
 	if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
@@ -281,30 +340,30 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		assign_map.apply(sig_b);
 		assign_map.apply(sig_y);
 
-		int mapped_a = map_signal(sig_a);
-		int mapped_b = map_signal(sig_b);
+		int mapped_a = map_signal(assign_map, sig_a);
+		int mapped_b = map_signal(assign_map, sig_b);
 
 		if (cell->type == ID($_AND_))
-			map_signal(sig_y, G(AND), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(AND), mapped_a, mapped_b);
 		else if (cell->type == ID($_NAND_))
-			map_signal(sig_y, G(NAND), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(NAND), mapped_a, mapped_b);
 		else if (cell->type == ID($_OR_))
-			map_signal(sig_y, G(OR), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(OR), mapped_a, mapped_b);
 		else if (cell->type == ID($_NOR_))
-			map_signal(sig_y, G(NOR), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(NOR), mapped_a, mapped_b);
 		else if (cell->type == ID($_XOR_))
-			map_signal(sig_y, G(XOR), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(XOR), mapped_a, mapped_b);
 		else if (cell->type == ID($_XNOR_))
-			map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(XNOR), mapped_a, mapped_b);
 		else if (cell->type == ID($_ANDNOT_))
-			map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(ANDNOT), mapped_a, mapped_b);
 		else if (cell->type == ID($_ORNOT_))
-			map_signal(sig_y, G(ORNOT), mapped_a, mapped_b);
+			map_signal(assign_map, sig_y, G(ORNOT), mapped_a, mapped_b);
 		else
 			log_abort();
 
 		module->remove(cell);
-		return;
+		return true;
 	}
 
 	if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
@@ -319,14 +378,14 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		assign_map.apply(sig_s);
 		assign_map.apply(sig_y);
 
-		int mapped_a = map_signal(sig_a);
-		int mapped_b = map_signal(sig_b);
-		int mapped_s = map_signal(sig_s);
+		int mapped_a = map_signal(assign_map, sig_a);
+		int mapped_b = map_signal(assign_map, sig_b);
+		int mapped_s = map_signal(assign_map, sig_s);
 
-		map_signal(sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
+		map_signal(assign_map, sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
 
 		module->remove(cell);
-		return;
+		return true;
 	}
 
 	if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
@@ -341,14 +400,14 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		assign_map.apply(sig_c);
 		assign_map.apply(sig_y);
 
-		int mapped_a = map_signal(sig_a);
-		int mapped_b = map_signal(sig_b);
-		int mapped_c = map_signal(sig_c);
+		int mapped_a = map_signal(assign_map, sig_a);
+		int mapped_b = map_signal(assign_map, sig_b);
+		int mapped_c = map_signal(assign_map, sig_c);
 
-		map_signal(sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
+		map_signal(assign_map, sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
 
 		module->remove(cell);
-		return;
+		return true;
 	}
 
 	if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
@@ -365,19 +424,21 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		assign_map.apply(sig_d);
 		assign_map.apply(sig_y);
 
-		int mapped_a = map_signal(sig_a);
-		int mapped_b = map_signal(sig_b);
-		int mapped_c = map_signal(sig_c);
-		int mapped_d = map_signal(sig_d);
+		int mapped_a = map_signal(assign_map, sig_a);
+		int mapped_b = map_signal(assign_map, sig_b);
+		int mapped_c = map_signal(assign_map, sig_c);
+		int mapped_d = map_signal(assign_map, sig_d);
 
-		map_signal(sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
+		map_signal(assign_map, sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
 
 		module->remove(cell);
-		return;
+		return true;
 	}
+
+	return false;
 }
 
-std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
+std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire)
 {
 	std::string abc_sname = abc_name.substr(1);
 	bool isnew = false;
@@ -416,7 +477,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
 	return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
 }
 
-void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts)
+void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts)
 {
 	if (f == nullptr)
 		return;
@@ -445,7 +506,13 @@ void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &w
 	fprintf(f, "}\n");
 }
 
-void handle_loops()
+void connect(AbcSigMap &assign_map, RTLIL::Module *module, const RTLIL::SigSig &conn)
+{
+	module->connect(conn);
+	assign_map.add(conn.first, conn.second);
+}
+
+void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
 {
 	// http://en.wikipedia.org/wiki/Topological_sorting
 	// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
@@ -550,7 +617,7 @@ void handle_loops()
 				first_line = false;
 			}
 
-			int id3 = map_signal(RTLIL::SigSpec(wire));
+			int id3 = map_signal(assign_map, RTLIL::SigSpec(wire));
 			signal_list[id1].is_port = true;
 			signal_list[id3].is_port = true;
 			log_assert(id3 == int(in_edges_count.size()));
@@ -569,7 +636,7 @@ void handle_loops()
 			}
 			edges[id1].swap(edges[id3]);
 
-			module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
+			connect(assign_map, module, RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
 			dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
 		}
 	}
@@ -646,13 +713,15 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
 
 struct abc_output_filter
 {
+	const AbcModuleState &state;
 	bool got_cr;
 	int escape_seq_state;
 	std::string linebuf;
 	std::string tempdir_name;
 	bool show_tempdir;
 
-	abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
+	abc_output_filter(const AbcModuleState& state, std::string tempdir_name, bool show_tempdir)
+		: state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir)
 	{
 		got_cr = false;
 		escape_seq_state = 0;
@@ -693,8 +762,8 @@ struct abc_output_filter
 		int pi, po;
 		if (sscanf(line.c_str(), "Start-point = pi%d.  End-point = po%d.", &pi, &po) == 2) {
 			log("ABC: Start-point = pi%d (%s).  End-point = po%d (%s).\n",
-					pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
-					po, po_map.count(po) ? po_map.at(po).c_str() : "???");
+					pi, state.pi_map.count(pi) ? state.pi_map.at(pi).c_str() : "???",
+					po, state.po_map.count(po) ? state.po_map.at(po).c_str() : "???");
 			return;
 		}
 
@@ -703,20 +772,12 @@ struct abc_output_filter
 	}
 };
 
-void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
-		std::vector<std::string> &liberty_files, std::vector<std::string> &genlib_files, std::string constr_file,
-		bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target,
-		std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector<std::string> &dont_use_cells)
+void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector<RTLIL::Cell*> &cells,
+	bool dff_mode, std::string clk_str)
 {
-	module = current_module;
+	initvals.set(&assign_map, module);
 	map_autoidx = autoidx++;
 
-	signal_map.clear();
-	signal_list.clear();
-	pi_map.clear();
-	po_map.clear();
-
 	if (clk_str != "$")
 	{
 		clk_polarity = true;
@@ -787,39 +848,39 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	if (dff_mode && clk_sig.empty())
 		log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
 
-	std::string tempdir_name;
-	if (cleanup) 
+	if (config.cleanup)
 		tempdir_name = get_base_tmpdir() + "/";
 	else
 		tempdir_name = "_tmp_";
 	tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
 	tempdir_name = make_temp_dir(tempdir_name);
 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
-			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
+			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str());
 
 	std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
 
-	if (!liberty_files.empty() || !genlib_files.empty()) {
+	if (!config.liberty_files.empty() || !config.genlib_files.empty()) {
 		std::string dont_use_args;
-		for (std::string dont_use_cell : dont_use_cells) {
+		for (std::string dont_use_cell : config.dont_use_cells) {
 			dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
 		}
 		bool first_lib = true;
-		for (std::string liberty_file : liberty_files) {
+		for (std::string liberty_file : config.liberty_files) {
 			abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args.c_str(), first_lib ? "" : "-m", liberty_file.c_str());
 			first_lib = false;
 		}
-		for (std::string liberty_file : genlib_files)
+		for (std::string liberty_file : config.genlib_files)
 			abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
-		if (!constr_file.empty())
-			abc_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
+		if (!config.constr_file.empty())
+			abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file.c_str());
 	} else
-	if (!lut_costs.empty())
+	if (!config.lut_costs.empty())
 		abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
 	else
 		abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
 
-	if (!script_file.empty()) {
+	if (!config.script_file.empty()) {
+		const std::string &script_file = config.script_file;
 		if (script_file[0] == '+') {
 			for (size_t i = 1; i < script_file.size(); i++)
 				if (script_file[i] == '\'')
@@ -830,37 +891,38 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					abc_script += script_file[i];
 		} else
 			abc_script += stringf("source %s", script_file.c_str());
-	} else if (!lut_costs.empty()) {
+	} else if (!config.lut_costs.empty()) {
 		bool all_luts_cost_same = true;
-		for (int this_cost : lut_costs)
-			if (this_cost != lut_costs.front())
+		for (int this_cost : config.lut_costs)
+			if (this_cost != config.lut_costs.front())
 				all_luts_cost_same = false;
-		abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
-		if (all_luts_cost_same && !fast_mode)
+		abc_script += config.fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
+		if (all_luts_cost_same && !config.fast_mode)
 			abc_script += "; lutpack {S}";
-	} else if (!liberty_files.empty() || !genlib_files.empty())
-		abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
-	else if (sop_mode)
-		abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
+	} else if (!config.liberty_files.empty() || !config.genlib_files.empty())
+		abc_script += config.constr_file.empty() ?
+			(config.fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (config.fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
+	else if (config.sop_mode)
+		abc_script += config.fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
 	else
-		abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
+		abc_script += config.fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
 
-	if (script_file.empty() && !delay_target.empty())
+	if (config.script_file.empty() && !config.delay_target.empty())
 		for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
 			abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
 
 	for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
-		abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
+		abc_script = abc_script.substr(0, pos) + config.delay_target + abc_script.substr(pos+3);
 
 	for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{I}", pos))
-		abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
+		abc_script = abc_script.substr(0, pos) + config.sop_inputs + abc_script.substr(pos+3);
 
 	for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{P}", pos))
-		abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
+		abc_script = abc_script.substr(0, pos) + config.sop_products + abc_script.substr(pos+3);
 
 	for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
-		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
-	if (abc_dress)
+		abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3);
+	if (config.abc_dress)
 		abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name.c_str());
 	abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
 	abc_script = add_echos_to_abc_cmd(abc_script);
@@ -895,34 +957,34 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	undef_bits_lost = 0;
 
 	had_init = false;
+	std::vector<RTLIL::Cell *> kept_cells;
 	for (auto c : cells)
-		extract_cell(c, keepff);
+		if (!extract_cell(assign_map, module, c, config.keepff))
+			kept_cells.push_back(c);
 
 	if (undef_bits_lost)
 		log("Replacing %d occurrences of constant undef bits with constant zero bits\n", undef_bits_lost);
 
-	for (auto wire : module->wires()) {
-		if (wire->port_id > 0 || wire->get_bool_attribute(ID::keep))
-			mark_port(wire);
-	}
-
-	for (auto cell : module->cells())
-	for (auto &port_it : cell->connections())
-		mark_port(port_it.second);
+	// Wires with port_id > 0 and connections to cells outside our cell set have already
+	// been accounted for via AbcSigVal::is_port. Now we just need to account for
+	// connections to cells inside our cell set that weren't removed by extract_cell().
+	for (auto cell : kept_cells)
+		for (auto &port_it : cell->connections())
+			mark_port(assign_map, port_it.second);
 
 	if (clk_sig.size() != 0)
-		mark_port(clk_sig);
+		mark_port(assign_map, clk_sig);
 
 	if (en_sig.size() != 0)
-		mark_port(en_sig);
+		mark_port(assign_map, en_sig);
 
 	if (arst_sig.size() != 0)
-		mark_port(arst_sig);
+		mark_port(assign_map, arst_sig);
 
 	if (srst_sig.size() != 0)
-		mark_port(srst_sig);
+		mark_port(assign_map, srst_sig);
 
-	handle_loops();
+	handle_loops(assign_map, module);
 
 	buffer = stringf("%s/input.blif", tempdir_name.c_str());
 	f = fopen(buffer.c_str(), "wt");
@@ -1095,21 +1157,21 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 			fprintf(f, "GATE MUX16  %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
 		fclose(f);
 
-		if (!lut_costs.empty()) {
+		if (!config.lut_costs.empty()) {
 			buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
 			f = fopen(buffer.c_str(), "wt");
 			if (f == nullptr)
 				log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
-			for (int i = 0; i < GetSize(lut_costs); i++)
-				fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
+			for (int i = 0; i < GetSize(config.lut_costs); i++)
+				fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i));
 			fclose(f);
 		}
 
-		buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
-		log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
+		buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str());
+		log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str());
 
 #ifndef YOSYS_LINK_ABC
-		abc_output_filter filt(tempdir_name, show_tempdir);
+		abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
 		int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
 #else
 		string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str());
@@ -1133,7 +1195,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		// These needs to be mutable, supposedly due to getopt
 		char *abc_argv[5];
 		string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
-		abc_argv[0] = strdup(exe_file.c_str());
+		abc_argv[0] = strdup(config.exe_file.c_str());
 		abc_argv[1] = strdup("-s");
 		abc_argv[2] = strdup("-f");
 		abc_argv[3] = strdup(tmp_script_name.c_str());
@@ -1150,199 +1212,160 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		fclose(old_stdout);
 		fclose(old_stderr);
 		std::ifstream temp_stdouterr_r(temp_stdouterr_name);
-		abc_output_filter filt(tempdir_name, show_tempdir);
+		abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
 		for (std::string line; std::getline(temp_stdouterr_r, line); )
 			filt.next_line(line + "\n");
 		temp_stdouterr_r.close();
 #endif
-		if (ret != 0)
+		if (ret != 0) {
 			log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
-
-		buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
-		std::ifstream ifs;
-		ifs.open(buffer);
-		if (ifs.fail())
-			log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
-
-		bool builtin_lib = liberty_files.empty() && genlib_files.empty();
-		RTLIL::Design *mapped_design = new RTLIL::Design;
-		parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, sop_mode);
-
-		ifs.close();
-
-		log_header(design, "Re-integrating ABC results.\n");
-		RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
-		if (mapped_mod == nullptr)
-			log_error("ABC output file does not contain a module `netlist'.\n");
-		for (auto w : mapped_mod->wires()) {
-			RTLIL::Wire *orig_wire = nullptr;
-			RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
-			if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
-				wire->attributes[ID::src] = orig_wire->attributes[ID::src];
-			if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
-			design->select(module, wire);
+			return;
 		}
+		did_run_abc = true;
+		return;
+	}
+	log("Don't call ABC as there is nothing to map.\n");
+}
 
-		SigMap mapped_sigmap(mapped_mod);
-		FfInitVals mapped_initvals(&mapped_sigmap, mapped_mod);
+void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module)
+{
+	if (!did_run_abc) {
+		return;
+	}
 
-		dict<std::string, int> cell_stats;
-		for (auto c : mapped_mod->cells())
+	std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
+	std::ifstream ifs;
+	ifs.open(buffer);
+	if (ifs.fail())
+		log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
+
+	bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
+	RTLIL::Design *mapped_design = new RTLIL::Design;
+	parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode);
+
+	ifs.close();
+
+	log_header(design, "Re-integrating ABC results.\n");
+	RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
+	if (mapped_mod == nullptr)
+		log_error("ABC output file does not contain a module `netlist'.\n");
+	for (auto w : mapped_mod->wires()) {
+		RTLIL::Wire *orig_wire = nullptr;
+		RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
+		if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
+			wire->attributes[ID::src] = orig_wire->attributes[ID::src];
+		if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
+		design->select(module, wire);
+	}
+
+	SigMap mapped_sigmap(mapped_mod);
+	FfInitVals mapped_initvals(&mapped_sigmap, mapped_mod);
+
+	dict<std::string, int> cell_stats;
+	for (auto c : mapped_mod->cells())
+	{
+		if (builtin_lib)
 		{
-			if (builtin_lib)
-			{
-				cell_stats[RTLIL::unescape_id(c->type)]++;
-				if (c->type.in(ID(ZERO), ID(ONE))) {
-					RTLIL::SigSig conn;
-					RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
-					conn.first = module->wire(name_y);
-					conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
-					module->connect(conn);
-					continue;
-				}
-				if (c->type == ID(BUF)) {
-					RTLIL::SigSig conn;
-					RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
-					RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
-					conn.first = module->wire(name_y);
-					conn.second = module->wire(name_a);
-					module->connect(conn);
-					continue;
-				}
-				if (c->type == ID(NOT)) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type.in(ID(MUX), ID(NMUX))) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::S, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type == ID(MUX4)) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type == ID(MUX8)) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type == ID(MUX16)) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
-							ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type.in(ID(AOI3), ID(OAI3))) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::C, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type.in(ID(AOI4), ID(OAI4))) {
-					RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::Y}) {
-						RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
-						cell->setPort(name, module->wire(remapped_name));
-					}
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type == ID(DFF)) {
-					log_assert(clk_sig.size() == 1);
-					FfData ff(module, &initvals, remap_name(c->name));
-					ff.width = 1;
-					ff.is_fine = true;
-					ff.has_clk = true;
-					ff.pol_clk = clk_polarity;
-					ff.sig_clk = clk_sig;
-					if (en_sig.size() != 0) {
-						log_assert(en_sig.size() == 1);
-						ff.has_ce = true;
-						ff.pol_ce = en_polarity;
-						ff.sig_ce = en_sig;
-					}
-					RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
-					if (had_init)
-						ff.val_init = init;
-					else
-						ff.val_init = State::Sx;
-					if (arst_sig.size() != 0) {
-						log_assert(arst_sig.size() == 1);
-						ff.has_arst = true;
-						ff.pol_arst = arst_polarity;
-						ff.sig_arst = arst_sig;
-						ff.val_arst = init;
-					}
-					if (srst_sig.size() != 0) {
-						log_assert(srst_sig.size() == 1);
-						ff.has_srst = true;
-						ff.pol_srst = srst_polarity;
-						ff.sig_srst = srst_sig;
-						ff.val_srst = init;
-					}
-					ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
-					ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
-					RTLIL::Cell *cell = ff.emit();
-					if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-					design->select(module, cell);
-					continue;
-				}
-			}
-			else
-				cell_stats[RTLIL::unescape_id(c->type)]++;
-
-			if (c->type.in(ID(_const0_), ID(_const1_))) {
+			cell_stats[RTLIL::unescape_id(c->type)]++;
+			if (c->type.in(ID(ZERO), ID(ONE))) {
 				RTLIL::SigSig conn;
-				conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
-				conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
-				module->connect(conn);
+				RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
+				conn.first = module->wire(name_y);
+				conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
+				connect(assign_map, module, conn);
 				continue;
 			}
-
-			if (c->type == ID(_dff_)) {
+			if (c->type == ID(BUF)) {
+				RTLIL::SigSig conn;
+				RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
+				RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
+				conn.first = module->wire(name_y);
+				conn.second = module->wire(name_a);
+				connect(assign_map, module, conn);
+				continue;
+			}
+			if (c->type == ID(NOT)) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type.in(ID(MUX), ID(NMUX))) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::S, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type == ID(MUX4)) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type == ID(MUX8)) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type == ID(MUX16)) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
+						ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type.in(ID(AOI3), ID(OAI3))) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::C, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type.in(ID(AOI4), ID(OAI4))) {
+				RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
+				if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+				for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::Y}) {
+					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
+					cell->setPort(name, module->wire(remapped_name));
+				}
+				design->select(module, cell);
+				continue;
+			}
+			if (c->type == ID(DFF)) {
 				log_assert(clk_sig.size() == 1);
 				FfData ff(module, &initvals, remap_name(c->name));
 				ff.width = 1;
@@ -1352,6 +1375,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 				ff.sig_clk = clk_sig;
 				if (en_sig.size() != 0) {
 					log_assert(en_sig.size() == 1);
+					ff.has_ce = true;
 					ff.pol_ce = en_polarity;
 					ff.sig_ce = en_sig;
 				}
@@ -1362,12 +1386,14 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					ff.val_init = State::Sx;
 				if (arst_sig.size() != 0) {
 					log_assert(arst_sig.size() == 1);
+					ff.has_arst = true;
 					ff.pol_arst = arst_polarity;
 					ff.sig_arst = arst_sig;
 					ff.val_arst = init;
 				}
 				if (srst_sig.size() != 0) {
 					log_assert(srst_sig.size() == 1);
+					ff.has_srst = true;
 					ff.pol_srst = srst_polarity;
 					ff.sig_srst = srst_sig;
 					ff.val_srst = init;
@@ -1379,70 +1405,117 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 				design->select(module, cell);
 				continue;
 			}
+		}
+		else
+			cell_stats[RTLIL::unescape_id(c->type)]++;
 
-			if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
-				SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
-				SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
-				module->connect(my_y, my_a);
-				continue;
+		if (c->type.in(ID(_const0_), ID(_const1_))) {
+			RTLIL::SigSig conn;
+			conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
+			conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
+			connect(assign_map, module, conn);
+			continue;
+		}
+
+		if (c->type == ID(_dff_)) {
+			log_assert(clk_sig.size() == 1);
+			FfData ff(module, &initvals, remap_name(c->name));
+			ff.width = 1;
+			ff.is_fine = true;
+			ff.has_clk = true;
+			ff.pol_clk = clk_polarity;
+			ff.sig_clk = clk_sig;
+			if (en_sig.size() != 0) {
+				log_assert(en_sig.size() == 1);
+				ff.pol_ce = en_polarity;
+				ff.sig_ce = en_sig;
 			}
-
-			RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
+			RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
+			if (had_init)
+				ff.val_init = init;
+			else
+				ff.val_init = State::Sx;
+			if (arst_sig.size() != 0) {
+				log_assert(arst_sig.size() == 1);
+				ff.pol_arst = arst_polarity;
+				ff.sig_arst = arst_sig;
+				ff.val_arst = init;
+			}
+			if (srst_sig.size() != 0) {
+				log_assert(srst_sig.size() == 1);
+				ff.pol_srst = srst_polarity;
+				ff.sig_srst = srst_sig;
+				ff.val_srst = init;
+			}
+			ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
+			ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
+			RTLIL::Cell *cell = ff.emit();
 			if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
-			cell->parameters = c->parameters;
-			for (auto &conn : c->connections()) {
-				RTLIL::SigSpec newsig;
-				for (auto &c : conn.second.chunks()) {
-					if (c.width == 0)
-						continue;
-					log_assert(c.width == 1);
-					newsig.append(module->wire(remap_name(c.wire->name)));
-				}
-				cell->setPort(conn.first, newsig);
-			}
 			design->select(module, cell);
+			continue;
 		}
 
-		for (auto conn : mapped_mod->connections()) {
-			if (!conn.first.is_fully_const())
-				conn.first = module->wire(remap_name(conn.first.as_wire()->name));
-			if (!conn.second.is_fully_const())
-				conn.second = module->wire(remap_name(conn.second.as_wire()->name));
-			module->connect(conn);
+		if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
+			SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
+			SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
+			connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
+			continue;
 		}
 
-		cell_stats.sort();
-		for (auto &it : cell_stats)
-			log("ABC RESULTS:   %15s cells: %8d\n", it.first.c_str(), it.second);
-		int in_wires = 0, out_wires = 0;
-		for (auto &si : signal_list)
-			if (si.is_port) {
-				char buffer[100];
-				snprintf(buffer, 100, "\\ys__n%d", si.id);
-				RTLIL::SigSig conn;
-				if (si.type != G(NONE)) {
-					conn.first = si.bit;
-					conn.second = module->wire(remap_name(buffer));
-					out_wires++;
-				} else {
-					conn.first = module->wire(remap_name(buffer));
-					conn.second = si.bit;
-					in_wires++;
-				}
-				module->connect(conn);
+		RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
+		if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+		cell->parameters = c->parameters;
+		for (auto &conn : c->connections()) {
+			RTLIL::SigSpec newsig;
+			for (auto &c : conn.second.chunks()) {
+				if (c.width == 0)
+					continue;
+				log_assert(c.width == 1);
+				newsig.append(module->wire(remap_name(c.wire->name)));
 			}
-		log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
-		log("ABC RESULTS:           input signals: %8d\n", in_wires);
-		log("ABC RESULTS:          output signals: %8d\n", out_wires);
-
-		delete mapped_design;
-	}
-	else
-	{
-		log("Don't call ABC as there is nothing to map.\n");
+			cell->setPort(conn.first, newsig);
+		}
+		design->select(module, cell);
 	}
 
-	if (cleanup)
+	for (auto conn : mapped_mod->connections()) {
+		if (!conn.first.is_fully_const())
+			conn.first = module->wire(remap_name(conn.first.as_wire()->name));
+		if (!conn.second.is_fully_const())
+			conn.second = module->wire(remap_name(conn.second.as_wire()->name));
+		connect(assign_map, module, conn);
+	}
+
+	cell_stats.sort();
+	for (auto &it : cell_stats)
+		log("ABC RESULTS:   %15s cells: %8d\n", it.first.c_str(), it.second);
+	int in_wires = 0, out_wires = 0;
+	for (auto &si : signal_list)
+		if (si.is_port) {
+			char buffer[100];
+			snprintf(buffer, 100, "\\ys__n%d", si.id);
+			RTLIL::SigSig conn;
+			if (si.type != G(NONE)) {
+				conn.first = si.bit;
+				conn.second = module->wire(remap_name(buffer));
+				out_wires++;
+			} else {
+				conn.first = module->wire(remap_name(buffer));
+				conn.second = si.bit;
+				in_wires++;
+			}
+			connect(assign_map, module, conn);
+		}
+	log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
+	log("ABC RESULTS:           input signals: %8d\n", in_wires);
+	log("ABC RESULTS:          output signals: %8d\n", out_wires);
+
+	delete mapped_design;
+}
+
+void AbcModuleState::finish()
+{
+	if (config.cleanup)
 	{
 		log("Removing temp directory.\n");
 		remove_directory(tempdir_name);
@@ -1451,6 +1524,47 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	log_pop();
 }
 
+// For every signal that connects cells from different sets, or a cell in a set to a cell not in any set,
+// mark it as a port in `assign_map`.
+void assign_cell_connection_ports(RTLIL::Module *module, const std::vector<std::vector<RTLIL::Cell *> *> &cell_sets,
+	AbcSigMap &assign_map)
+{
+	pool<RTLIL::Cell *> cells_in_no_set;
+	for (RTLIL::Cell *cell : module->cells()) {
+		cells_in_no_set.insert(cell);
+	}
+	// For every canonical signal in `assign_map`, the index of the set it is connected to,
+	// or -1 if it connects a cell in one set to a cell in another set or not in any set.
+	dict<SigBit, int> signal_cell_set;
+	for (int i = 0; i < int(cell_sets.size()); ++i) {
+		for (RTLIL::Cell *cell : *cell_sets[i]) {
+			cells_in_no_set.erase(cell);
+			for (auto &port_it : cell->connections()) {
+				for (SigBit bit : port_it.second) {
+					assign_map.apply(bit);
+					auto it = signal_cell_set.find(bit);
+					if (it == signal_cell_set.end())
+						signal_cell_set[bit] = i;
+					else if (it->second >= 0 && it->second != i) {
+						it->second = -1;
+						assign_map.addVal(bit, AbcSigVal(true));
+					}
+				}
+			}
+		}
+	}
+	for (RTLIL::Cell *cell : cells_in_no_set) {
+		for (auto &port_it : cell->connections()) {
+			for (SigBit bit : port_it.second) {
+				assign_map.apply(bit);
+				auto it = signal_cell_set.find(bit);
+				if (it != signal_cell_set.end() && it->second >= 0)
+					assign_map.addVal(bit, AbcSigVal(true));
+			}
+		}
+	}
+}
+
 struct AbcPass : public Pass {
 	AbcPass() : Pass("abc", "use ABC for technology mapping") { }
 	void help() override
@@ -1652,71 +1766,52 @@ struct AbcPass : public Pass {
 		log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
 		log_push();
 
-		assign_map.clear();
-		signal_list.clear();
-		signal_map.clear();
-		initvals.clear();
-		pi_map.clear();
-		po_map.clear();
-
-		std::string exe_file = yosys_abc_executable;
-		std::string script_file, default_liberty_file, constr_file, clk_str;
-		std::vector<std::string> liberty_files, genlib_files, dont_use_cells;
-		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
-		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
-		bool show_tempdir = false, sop_mode = false;
-		bool abc_dress = false;
-		vector<int> lut_costs;
-		markgroups = false;
-
-		map_mux4 = false;
-		map_mux8 = false;
-		map_mux16 = false;
-		enabled_gates.clear();
-		cmos_cost = false;
+		AbcConfig config;
 
 		// get arguments from scratchpad first, then override by command arguments
 		std::string lut_arg, luts_arg, g_arg;
-		exe_file = design->scratchpad_get_string("abc.exe", exe_file /* inherit default value if not set */);
-		script_file = design->scratchpad_get_string("abc.script", script_file);
-		default_liberty_file = design->scratchpad_get_string("abc.liberty", default_liberty_file);
-		constr_file = design->scratchpad_get_string("abc.constr", constr_file);
+		config.exe_file = design->scratchpad_get_string("abc.exe", yosys_abc_executable /* inherit default value if not set */);
+		config.script_file = design->scratchpad_get_string("abc.script", "");
+		std::string default_liberty_file = design->scratchpad_get_string("abc.liberty", "");
+		config.constr_file = design->scratchpad_get_string("abc.constr", "");
 		if (design->scratchpad.count("abc.D")) {
-			delay_target = "-D " + design->scratchpad_get_string("abc.D");
+			config.delay_target = "-D " + design->scratchpad_get_string("abc.D");
 		}
 		if (design->scratchpad.count("abc.I")) {
-			sop_inputs = "-I " + design->scratchpad_get_string("abc.I");
+			config.sop_inputs = "-I " + design->scratchpad_get_string("abc.I");
 		}
 		if (design->scratchpad.count("abc.P")) {
-			sop_products = "-P " + design->scratchpad_get_string("abc.P");
+			config.sop_products = "-P " + design->scratchpad_get_string("abc.P");
 		}
 		if (design->scratchpad.count("abc.S")) {
-			lutin_shared = "-S " + design->scratchpad_get_string("abc.S");
+			config.lutin_shared = "-S " + design->scratchpad_get_string("abc.S");
+		} else {
+			config.lutin_shared = "-S 1";
 		}
 		lut_arg = design->scratchpad_get_string("abc.lut", lut_arg);
 		luts_arg = design->scratchpad_get_string("abc.luts", luts_arg);
-		sop_mode = design->scratchpad_get_bool("abc.sop", sop_mode);
+		config.sop_mode = design->scratchpad_get_bool("abc.sop", false);
 		map_mux4 = design->scratchpad_get_bool("abc.mux4", map_mux4);
 		map_mux8 = design->scratchpad_get_bool("abc.mux8", map_mux8);
 		map_mux16 = design->scratchpad_get_bool("abc.mux16", map_mux16);
-		abc_dress = design->scratchpad_get_bool("abc.dress", abc_dress);
+		config.abc_dress = design->scratchpad_get_bool("abc.dress", false);
 		g_arg = design->scratchpad_get_string("abc.g", g_arg);
 
-		fast_mode = design->scratchpad_get_bool("abc.fast", fast_mode);
-		dff_mode = design->scratchpad_get_bool("abc.dff", dff_mode);
+		config.fast_mode = design->scratchpad_get_bool("abc.fast", false);
+		bool dff_mode = design->scratchpad_get_bool("abc.dff", false);
+		std::string clk_str;
 		if (design->scratchpad.count("abc.clk")) {
 			clk_str = design->scratchpad_get_string("abc.clk");
 			dff_mode = true;
 		}
-		keepff = design->scratchpad_get_bool("abc.keepff", keepff);
-		cleanup = !design->scratchpad_get_bool("abc.nocleanup", !cleanup);
-		keepff = design->scratchpad_get_bool("abc.keepff", keepff);
-		show_tempdir = design->scratchpad_get_bool("abc.showtmp", show_tempdir);
+		config.keepff = design->scratchpad_get_bool("abc.keepff", false);
+		config.cleanup = !design->scratchpad_get_bool("abc.nocleanup", false);
+		config.show_tempdir = design->scratchpad_get_bool("abc.showtmp", false);
 		markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups);
 
 		if (design->scratchpad_get_bool("abc.debug")) {
-			cleanup = false;
-			show_tempdir = true;
+			config.cleanup = false;
+			config.show_tempdir = true;
 		}
 
 		size_t argidx, g_argidx = -1;
@@ -1733,43 +1828,43 @@ struct AbcPass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
 			if (arg == "-exe" && argidx+1 < args.size()) {
-				exe_file = args[++argidx];
+				config.exe_file = args[++argidx];
 				continue;
 			}
 			if (arg == "-script" && argidx+1 < args.size()) {
-				script_file = args[++argidx];
+				config.script_file = args[++argidx];
 				continue;
 			}
 			if (arg == "-liberty" && argidx+1 < args.size()) {
-				liberty_files.push_back(args[++argidx]);
+				config.liberty_files.push_back(args[++argidx]);
 				continue;
 			}
 			if (arg == "-dont_use" && argidx+1 < args.size()) {
-				dont_use_cells.push_back(args[++argidx]);
+				config.dont_use_cells.push_back(args[++argidx]);
 				continue;
 			}
 			if (arg == "-genlib" && argidx+1 < args.size()) {
-				genlib_files.push_back(args[++argidx]);
+				config.genlib_files.push_back(args[++argidx]);
 				continue;
 			}
 			if (arg == "-constr" && argidx+1 < args.size()) {
-				constr_file = args[++argidx];
+				config.constr_file = args[++argidx];
 				continue;
 			}
 			if (arg == "-D" && argidx+1 < args.size()) {
-				delay_target = "-D " + args[++argidx];
+				config.delay_target = "-D " + args[++argidx];
 				continue;
 			}
 			if (arg == "-I" && argidx+1 < args.size()) {
-				sop_inputs = "-I " + args[++argidx];
+				config.sop_inputs = "-I " + args[++argidx];
 				continue;
 			}
 			if (arg == "-P" && argidx+1 < args.size()) {
-				sop_products = "-P " + args[++argidx];
+				config.sop_products = "-P " + args[++argidx];
 				continue;
 			}
 			if (arg == "-S" && argidx+1 < args.size()) {
-				lutin_shared = "-S " + args[++argidx];
+				config.lutin_shared = "-S " + args[++argidx];
 				continue;
 			}
 			if (arg == "-lut" && argidx+1 < args.size()) {
@@ -1781,7 +1876,7 @@ struct AbcPass : public Pass {
 				continue;
 			}
 			if (arg == "-sop") {
-				sop_mode = true;
+				config.sop_mode = true;
 				continue;
 			}
 			if (arg == "-mux4") {
@@ -1797,7 +1892,7 @@ struct AbcPass : public Pass {
 				continue;
 			}
 			if (arg == "-dress") {
-				abc_dress = true;
+				config.abc_dress = true;
 				continue;
 			}
 			if (arg == "-g" && argidx+1 < args.size()) {
@@ -1809,7 +1904,7 @@ struct AbcPass : public Pass {
 				continue;
 			}
 			if (arg == "-fast") {
-				fast_mode = true;
+				config.fast_mode = true;
 				continue;
 			}
 			if (arg == "-dff") {
@@ -1822,15 +1917,15 @@ struct AbcPass : public Pass {
 				continue;
 			}
 			if (arg == "-keepff") {
-				keepff = true;
+				config.keepff = true;
 				continue;
 			}
 			if (arg == "-nocleanup") {
-				cleanup = false;
+				config.cleanup = false;
 				continue;
 			}
 			if (arg == "-showtmp") {
-				show_tempdir = true;
+				config.show_tempdir = true;
 				continue;
 			}
 			if (arg == "-markgroups") {
@@ -1841,25 +1936,25 @@ struct AbcPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (genlib_files.empty() && liberty_files.empty() && !default_liberty_file.empty())
-			liberty_files.push_back(default_liberty_file);
+		if (config.genlib_files.empty() && config.liberty_files.empty() && !default_liberty_file.empty())
+			config.liberty_files.push_back(default_liberty_file);
 
-		rewrite_filename(script_file);
-		if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
-			script_file = std::string(pwd) + "/" + script_file;
-		for (int i = 0; i < GetSize(liberty_files); i++) {
-			rewrite_filename(liberty_files[i]);
-			if (!liberty_files[i].empty() && !is_absolute_path(liberty_files[i]))
-				liberty_files[i] = std::string(pwd) + "/" + liberty_files[i];
+		rewrite_filename(config.script_file);
+		if (!config.script_file.empty() && !is_absolute_path(config.script_file) && config.script_file[0] != '+')
+			config.script_file = std::string(pwd) + "/" + config.script_file;
+		for (int i = 0; i < GetSize(config.liberty_files); i++) {
+			rewrite_filename(config.liberty_files[i]);
+			if (!config.liberty_files[i].empty() && !is_absolute_path(config.liberty_files[i]))
+				config.liberty_files[i] = std::string(pwd) + "/" + config.liberty_files[i];
 		}
-		for (int i = 0; i < GetSize(genlib_files); i++) {
-			rewrite_filename(genlib_files[i]);
-			if (!genlib_files[i].empty() && !is_absolute_path(genlib_files[i]))
-				genlib_files[i] = std::string(pwd) + "/" + genlib_files[i];
+		for (int i = 0; i < GetSize(config.genlib_files); i++) {
+			rewrite_filename(config.genlib_files[i]);
+			if (!config.genlib_files[i].empty() && !is_absolute_path(config.genlib_files[i]))
+				config.genlib_files[i] = std::string(pwd) + "/" + config.genlib_files[i];
 		}
-		rewrite_filename(constr_file);
-		if (!constr_file.empty() && !is_absolute_path(constr_file))
-			constr_file = std::string(pwd) + "/" + constr_file;
+		rewrite_filename(config.constr_file);
+		if (!config.constr_file.empty() && !is_absolute_path(config.constr_file))
+			config.constr_file = std::string(pwd) + "/" + config.constr_file;
 
 		// handle -lut argument
 		if (!lut_arg.empty()) {
@@ -1872,24 +1967,24 @@ struct AbcPass : public Pass {
 				lut_mode = atoi(lut_arg.c_str());
 				lut_mode2 = lut_mode;
 			}
-			lut_costs.clear();
+			config.lut_costs.clear();
 			for (int i = 0; i < lut_mode; i++)
-				lut_costs.push_back(1);
+				config.lut_costs.push_back(1);
 			for (int i = lut_mode; i < lut_mode2; i++)
-				lut_costs.push_back(2 << (i - lut_mode));
+				config.lut_costs.push_back(2 << (i - lut_mode));
 		}
 		//handle -luts argument
 		if (!luts_arg.empty()){
-			lut_costs.clear();
+			config.lut_costs.clear();
 			for (auto &tok : split_tokens(luts_arg, ",")) {
 				auto parts = split_tokens(tok, ":");
-				if (GetSize(parts) == 0 && !lut_costs.empty())
-					lut_costs.push_back(lut_costs.back());
+				if (GetSize(parts) == 0 && !config.lut_costs.empty())
+					config.lut_costs.push_back(config.lut_costs.back());
 				else if (GetSize(parts) == 1)
-					lut_costs.push_back(atoi(parts.at(0).c_str()));
+					config.lut_costs.push_back(atoi(parts.at(0).c_str()));
 				else if (GetSize(parts) == 2)
-					while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str()))
-						lut_costs.push_back(atoi(parts.at(1).c_str()));
+					while (GetSize(config.lut_costs) < std::atoi(parts.at(0).c_str()))
+						config.lut_costs.push_back(atoi(parts.at(1).c_str()));
 				else
 					log_cmd_error("Invalid -luts syntax.\n");
 			}
@@ -2020,9 +2115,9 @@ struct AbcPass : public Pass {
 			}
 		}
 
-		if (!lut_costs.empty() && !(liberty_files.empty() && genlib_files.empty()))
+		if (!config.lut_costs.empty() && !(config.liberty_files.empty() && config.genlib_files.empty()))
 			log_cmd_error("Got -lut and -liberty/-genlib! These two options are exclusive.\n");
-		if (!constr_file.empty() && (liberty_files.empty() && genlib_files.empty()))
+		if (!config.constr_file.empty() && (config.liberty_files.empty() && config.genlib_files.empty()))
 			log_cmd_error("Got -constr but no -liberty/-genlib!\n");
 
 		if (enabled_gates.empty()) {
@@ -2049,12 +2144,21 @@ struct AbcPass : public Pass {
 				continue;
 			}
 
+			AbcSigMap assign_map;
 			assign_map.set(mod);
-			initvals.set(&assign_map, mod);
+
+			for (auto wire : mod->wires())
+				if (wire->port_id > 0)
+					assign_map.addVal(SigSpec(wire), AbcSigVal(true));
 
 			if (!dff_mode || !clk_str.empty()) {
-				abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress, dont_use_cells);
+				std::vector<RTLIL::Cell*> cells = mod->selected_cells();
+				assign_cell_connection_ports(mod, {&cells}, assign_map);
+
+				AbcModuleState state(config);
+				state.abc_module(design, mod, assign_map, cells, dff_mode, clk_str);
+				state.extract(assign_map, design, mod);
+				state.finish();
 				continue;
 			}
 
@@ -2074,6 +2178,8 @@ struct AbcPass : public Pass {
 			dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
 			dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
 
+			FfInitVals initvals;
+			initvals.set(&assign_map, mod);
 			for (auto cell : all_cells)
 			{
 				clkdomain_t key;
@@ -2206,28 +2312,28 @@ struct AbcPass : public Pass {
 						std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
 						std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
 
+			{
+				std::vector<std::vector<RTLIL::Cell*>*> cell_sets;
+				for (auto &it : assigned_cells)
+					cell_sets.push_back(&it.second);
+				assign_cell_connection_ports(mod, cell_sets, assign_map);
+			}
 			for (auto &it : assigned_cells) {
-				clk_polarity = std::get<0>(it.first);
-				clk_sig = assign_map(std::get<1>(it.first));
-				en_polarity = std::get<2>(it.first);
-				en_sig = assign_map(std::get<3>(it.first));
-				arst_polarity = std::get<4>(it.first);
-				arst_sig = assign_map(std::get<5>(it.first));
-				srst_polarity = std::get<6>(it.first);
-				srst_sig = assign_map(std::get<7>(it.first));
-				abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress, dont_use_cells);
-				assign_map.set(mod);
+				AbcModuleState state(config);
+				state.clk_polarity = std::get<0>(it.first);
+				state.clk_sig = assign_map(std::get<1>(it.first));
+				state.en_polarity = std::get<2>(it.first);
+				state.en_sig = assign_map(std::get<3>(it.first));
+				state.arst_polarity = std::get<4>(it.first);
+				state.arst_sig = assign_map(std::get<5>(it.first));
+				state.srst_polarity = std::get<6>(it.first);
+				state.srst_sig = assign_map(std::get<7>(it.first));
+				state.abc_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$");
+				state.extract(assign_map, design, mod);
+				state.finish();
 			}
 		}
 
-		assign_map.clear();
-		signal_list.clear();
-		signal_map.clear();
-		initvals.clear();
-		pi_map.clear();
-		po_map.clear();
-
 		log_pop();
 	}
 } AbcPass;