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setundef: more tests! and wire selection in -init mode
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c23ba3f917
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3 changed files with 24 additions and 7 deletions
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@ -364,11 +364,19 @@ struct SetundefPass : public Pass {
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pool<SigBit> ffbits;
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pool<Wire*> initwires;
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for (auto cell : module->selected_cells())
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for (auto cell : module->cells())
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{
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if (!cell->is_builtin_ff())
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continue;
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bool cell_selected = design->selected(module, cell);
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bool wire_selected = false;
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for (auto bit : sigmap(cell->getPort(ID::Q)))
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if (bit.wire && design->selected(module, bit.wire))
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wire_selected = true;
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if (!cell_selected && !wire_selected)
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continue;
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for (auto bit : sigmap(cell->getPort(ID::Q)))
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ffbits.insert(bit);
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}
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