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verific: Pass top modules to static elaboration when using hierarchy

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This commit is contained in:
Jannis Harder 2023-10-05 16:40:43 +02:00
parent 23b9e61c47
commit 47a4b790f8
1 changed files with 54 additions and 34 deletions
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24
frontends/verific/verific.cc
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@ -2495,15 +2495,20 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str());
if (top.empty()) {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
#endif
if (top.empty()) {
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
}
else {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{
Array veri_modules, vhdl_units;
if (veri_lib) {
@ -2524,6 +2529,10 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
}
}
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (!static_elaborate)
#endif
{
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
@ -2531,6 +2540,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
veri_modules.InsertLast(veri_module);
}
}
}
#ifdef VERIFIC_VHDL_SUPPORT
if (vhdl_lib) {
@ -2539,8 +2549,18 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
vhdl_units.InsertLast(vhdl_unit);
}
#endif
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
verific_error_msg.clear();
continue;
}
#endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
}
}
Netlist *nl;
int i;