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verific: Pass top modules to static elaboration when using hierarchy

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This commit is contained in:
Jannis Harder 2023-10-05 16:40:43 +02:00
parent 23b9e61c47
commit 47a4b790f8
1 changed files with 54 additions and 34 deletions
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88
frontends/verific/verific.cc
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@ -2495,51 +2495,71 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
for (const auto &i : parameters) for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str()); verific_params.Insert(i.first.c_str(), i.second.c_str());
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
#endif
if (top.empty()) { if (top.empty()) {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
#endif
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params); netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
} }
else { else {
Array veri_modules, vhdl_units;
if (veri_lib) { #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
if (veri_module) { #endif
veri_modules.InsertLast(veri_module); {
if (veri_module->IsConfiguration()) { Array veri_modules, vhdl_units;
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); if (veri_lib) {
VeriLibrary *lib = veri_module->GetLibrary() ; VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
if (module_name && module_name->IsHierName()) { if (veri_module) {
VeriName *prefix = module_name->GetPrefix() ; veri_modules.InsertLast(veri_module);
const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (veri_module->IsConfiguration()) {
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
if (lib && module_name)
top = lib->GetModule(module_name->GetName(), 1)->GetName();
}
}
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (!static_elaborate)
#endif
{
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
} }
if (lib && module_name)
top = lib->GetModule(module_name->GetName(), 1)->GetName();
} }
} }
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
if (!veri_module->IsRootModule()) continue;
veri_modules.InsertLast(veri_module);
}
}
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
if (vhdl_lib) { if (vhdl_lib) {
VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
if (vhdl_unit) if (vhdl_unit)
vhdl_units.InsertLast(vhdl_unit); vhdl_units.InsertLast(vhdl_unit);
} }
#endif #endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
verific_error_msg.clear();
continue;
}
#endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
}
} }
Netlist *nl; Netlist *nl;