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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required

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This commit is contained in:
Eddie Hung 2020-01-09 10:03:09 -08:00
commit 47a1fd3f4a
1 changed files with 4 additions and 8 deletions
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12
frontends/aiger/aigerparse.cc
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@ -756,12 +756,6 @@ void AigerReader::post_process()
} }
for (uint32_t i = 0; i < flopNum; i++) { for (uint32_t i = 0; i < flopNum; i++) {
log_assert(co_count < outputs.size());
Wire *wire = outputs[co_count++];
log_assert(wire);
log_assert(wire->port_output);
wire->port_output = false;
RTLIL::Wire *d = outputs[outputs.size() - flopNum + i]; RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
log_assert(d); log_assert(d);
log_assert(d->port_output); log_assert(d->port_output);
@ -803,6 +797,7 @@ void AigerReader::post_process()
wire->port_input = false; wire->port_input = false;
module->connect(wire, existing); module->connect(wire, existing);
} }
log_debug(" -> %s\n", log_id(escaped_s));
} }
else if (index > 0) { else if (index > 0) {
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@ -816,8 +811,8 @@ void AigerReader::post_process()
module->connect(wire, existing); module->connect(wire, existing);
wire->port_input = false; wire->port_input = false;
} }
log_debug(" -> %s\n", log_id(indexed_name));
} }
log_debug(" -> %s\n", log_id(wire));
} }
else if (type == "output") { else if (type == "output") {
log_assert(static_cast<unsigned>(variable + co_count) < outputs.size()); log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
@ -839,6 +834,7 @@ void AigerReader::post_process()
module->connect(wire, existing); module->connect(wire, existing);
wire = existing; wire = existing;
} }
log_debug(" -> %s\n", log_id(escaped_s));
} }
else if (index > 0) { else if (index > 0) {
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@ -852,8 +848,8 @@ void AigerReader::post_process()
module->connect(wire, existing); module->connect(wire, existing);
wire->port_output = false; wire->port_output = false;
} }
log_debug(" -> %s\n", log_id(indexed_name));
} }
log_debug(" -> %s\n", log_id(wire));
int init; int init;
mf >> init; mf >> init;
if (init < 2) if (init < 2)