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Remove not needed tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:20:35 +02:00
parent 5603595e5c
commit 477702b8c9
4 changed files with 0 additions and 52 deletions
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19
tests/arch/ice40/alu.v
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@ -1,19 +0,0 @@
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule

11
tests/arch/ice40/alu.ys
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read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 62 t:SB_CARRY
select -assert-count 32 t:SB_DFF
select -assert-count 655 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D

13
tests/arch/ice40/div_mod.v
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module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x % y;
assign B = x / y;
endmodule

9
tests/arch/ice40/div_mod.ys
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@ -1,9 +0,0 @@
read_verilog div_mod.v
hierarchy -top top
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 59 t:SB_LUT4
select -assert-count 41 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D