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Merge pull request #5346 from YosysHQ/emil/verilog-codeowner

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CODEOWNERS: add myself for read_verilog and AST
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Emil J 2025-09-15 17:38:00 +02:00 • committed by GitHub
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@ -30,8 +30,8 @@ docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty
# These still override previous lines, so be careful not to
# accidentally disable any of the above rules.
frontends/verilog/ @zachjs
frontends/ast/ @zachjs
frontends/verilog/ @widlarizer
frontends/ast/ @widlarizer
techlibs/intel_alm/ @Ravenslofty
techlibs/gowin/ @pepijndevos