From 474ed28aee995131f8ece02090c648d931054055 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 14 Mar 2024 08:40:14 +0100 Subject: [PATCH] added no-rw-check, and new rfb models --- techlibs/nanoxplore/Makefile.inc | 6 +++- techlibs/nanoxplore/rf_rams_l.txt | 15 ++++++++ techlibs/nanoxplore/rf_rams_m.txt | 15 ++++++++ techlibs/nanoxplore/rf_rams_map_l.v | 30 ++++++++++++++++ techlibs/nanoxplore/rf_rams_map_m.v | 30 ++++++++++++++++ techlibs/nanoxplore/rf_rams_map_u.v | 46 ++++++++++++++++++++++--- techlibs/nanoxplore/synth_nanoxplore.cc | 31 +++++++++++------ 7 files changed, 158 insertions(+), 15 deletions(-) create mode 100644 techlibs/nanoxplore/rf_rams_l.txt create mode 100644 techlibs/nanoxplore/rf_rams_m.txt create mode 100644 techlibs/nanoxplore/rf_rams_map_l.v create mode 100644 techlibs/nanoxplore/rf_rams_map_m.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 40e730cbe..cae2817b3 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -16,5 +16,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) -$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) diff --git a/techlibs/nanoxplore/rf_rams_l.txt b/techlibs/nanoxplore/rf_rams_l.txt new file mode 100644 index 000000000..112655184 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_l.txt @@ -0,0 +1,15 @@ +ram distributed $__NX_RFB_L_ { + abits 6; + width 16; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port sr "R" { + clock anyedge; + rden; + } +} diff --git a/techlibs/nanoxplore/rf_rams_m.txt b/techlibs/nanoxplore/rf_rams_m.txt new file mode 100644 index 000000000..d872405a3 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_m.txt @@ -0,0 +1,15 @@ +ram distributed $__NX_RFB_M_ { + abits 6; + width 16; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port sr "R" { + clock anyedge; + rden; + } +} diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v new file mode 100644 index 000000000..e529ce1e1 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_l.v @@ -0,0 +1,30 @@ +module $__NX_RFB_L_ ( + input PORT_W_CLK, + input PORT_W_WR_EN, + input [5:0] PORT_W_ADDR, + input [15:0] PORT_W_WR_DATA, + input PORT_R_CLK, + input PORT_R_RD_EN, + input [5:0] PORT_R_ADDR, + output [15:0] PORT_R_RD_DATA, +); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + parameter PORT_R_CLK_POL = 1'b1; + + NX_RFB_L_WRAP #( + .mode(0), + .mem_ctxt(INIT), + .rck_edge(~PORT_R_CLK_POL), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .RCK(PORT_R_CLK), + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .RE(PORT_R_RD_EN), + .WE(PORT_W_WR_EN), + .O(PORT_R_RD_DATA) + ); +endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v new file mode 100644 index 000000000..a64dc3388 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_m.v @@ -0,0 +1,30 @@ +module $__NX_RFB_M_ ( + input PORT_W_CLK, + input PORT_W_WR_EN, + input [5:0] PORT_W_ADDR, + input [15:0] PORT_W_WR_DATA, + input PORT_R_CLK, + input PORT_R_RD_EN, + input [5:0] PORT_R_ADDR, + output [15:0] PORT_R_RD_DATA, +); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + parameter PORT_R_CLK_POL = 1'b1; + + NX_RFB_M_WRAP #( + .mode(0), + .mem_ctxt(INIT), + .rck_edge(~PORT_R_CLK_POL), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .RCK(PORT_R_CLK), + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .RE(PORT_R_RD_EN), + .WE(PORT_W_WR_EN), + .O(PORT_R_RD_DATA) + ); +endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v index 397dd0fcd..94d5df097 100644 --- a/techlibs/nanoxplore/rf_rams_map_u.v +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -1,12 +1,50 @@ -module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); +module $__NX_XRFB_64x18_ ( + input PORT_W_CLK, + input [5:0] PORT_W_ADDR, + input [5:0] PORT_R_ADDR, + input [17:0] PORT_W_WR_DATA, + input PORT_W_WR_EN, + output [17:0] PORT_R_RD_DATA +); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); + + NX_XRFB_64x18 #( + .mem_ctxt(INIT), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WEA(1'b1), + .O(PORT_R_RD_DATA) + ); endmodule -module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); +module $__NX_XRFB_32x36_ ( + input PORT_W_CLK, + input [4:0] PORT_W_ADDR, + input [4:0] PORT_R_ADDR, + input [35:0] PORT_W_WR_DATA, + input PORT_W_WR_EN, + output [35:0] PORT_R_RD_DATA +); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); + + NX_XRFB_32x36 #( + .mem_ctxt(INIT), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WEA(1'b1), + .O(PORT_R_RD_DATA) + ); endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index f6e507e62..23a2af278 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -85,6 +85,11 @@ struct SynthNanoXplorePass : public ScriptPass log(" -iopad\n"); log(" insert IO buffers\n"); log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -92,8 +97,8 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad; - std::string postfix, rf_postfix; + bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad, no_rw_check; + std::string postfix; void clear_flags() override { @@ -107,8 +112,8 @@ struct SynthNanoXplorePass : public ScriptPass nobram = false; nodsp = false; iopad = false; + no_rw_check = false; postfix = ""; - rf_postfix = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -171,6 +176,10 @@ struct SynthNanoXplorePass : public ScriptPass iopad = true; continue; } + if (args[argidx] == "-no-rw-check") { + no_rw_check = true; + continue; + } break; } extra_args(args, argidx, design); @@ -182,16 +191,12 @@ struct SynthNanoXplorePass : public ScriptPass if (family == "ultra") { postfix = "_u"; - rf_postfix = "_u"; } else if (family == "u300") { postfix = "_u"; - rf_postfix = "_u"; } else if (family == "medium") { postfix = "_m"; - rf_postfix = "_l"; } else if (family == "large") { postfix = "_l"; - rf_postfix = "_l"; } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); @@ -208,6 +213,12 @@ struct SynthNanoXplorePass : public ScriptPass void script() override { + std::string no_rw_check_opt = ""; + if (no_rw_check) + no_rw_check_opt = " -no-rw-check"; + if (help_mode) + no_rw_check_opt = " [-no-rw-check]"; + if (check_label("begin")) { run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); @@ -238,7 +249,7 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); run("alumacc"); run("opt"); - run("memory -nomap"); + run("memory -nomap" + no_rw_check_opt); run("opt_clean"); } @@ -251,8 +262,8 @@ struct SynthNanoXplorePass : public ScriptPass args += " -no-auto-distributed"; if (help_mode) args += " [-no-auto-block] [-no-auto-distributed]"; - run("memory_libmap -lib +/nanoxplore/rf_rams"+ rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); - run("techmap -map +/nanoxplore/rf_rams_map"+ rf_postfix+ ".v -map +/nanoxplore/brams_map.v"); + run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); + run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*"); }