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Tested and working altsyncarm without init files

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This commit is contained in:
dh73 2017-10-01 19:59:45 -05:00
parent e480847753
commit 4718e65763
2 changed files with 59 additions and 57 deletions
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28
techlibs/intel/common/brams_map.v
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@ -31,22 +31,16 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 36 ? 9:
'bx;
localparam NUMWORDS = CFG_DBITS == 1 ? "8192":
CFG_DBITS == 2 ? "4096":
CFG_DBITS == 4 ? "2048":
CFG_DBITS == 8 ? "1024":
CFG_DBITS == 9 ? "1024":
CFG_DBITS == 16 ? "512":
CFG_DBITS == 18 ? "512":
CFG_DBITS == 32 ? "256":
CFG_DBITS == 36 ? "256":
localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? 2048:
CFG_DBITS == 8 ? 1024:
CFG_DBITS == 9 ? 1024:
CFG_DBITS == 16 ? 512:
CFG_DBITS == 18 ? 512:
CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? 256:
'bx;
/* Killing some stupid warnings and assignations*/
/* generate
if( MODE == 1 ) begin
assign B1DATA_t = ({34{1'b0},B1DATA[0]});
end
endgenerate*/
altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
.clock_enable_input_a ("ALTERNATE" ),
@ -63,6 +57,10 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.lpm_type ("altsyncram" ),
.init_type ("unused" ),
.ram_block_type ("AUTO" ),
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.power_up_uninitialized ("FALSE"),
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_byteena_a (1), // Forced value
.numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ),
.widthad_b ( CFG_ABITS ),

4
techlibs/intel/common/m9k_bb.v
View file

@ -36,6 +36,10 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;