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Added SAT generator and simple sat_solve command

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This commit is contained in:
Clifford Wolf 2013-06-07 13:59:13 +02:00
parent 3371563f2f
commit 46fbe9d262
7 changed files with 400 additions and 3 deletions
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5
frontends/verilog/const2ast.cc
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@ -186,12 +186,11 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
break;
default:
goto error;
return NULL;
}
return AstNode::mkconst_bits(data, is_signed);
}
error:
log_error("Value conversion failed: `%s'\n", code.c_str());
return NULL;
}