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abc9_map: drop padding in box connections

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This commit is contained in:
Eddie Hung 2020-01-06 15:14:54 -08:00
parent 8d0cc654a4
commit 46ed507b93
1 changed files with 35 additions and 32 deletions
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67
passes/techmap/abc9_map.cc
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@ -435,29 +435,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
} }
if (existing_cell) {
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
}
else {
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
}
auto abc9_box = cell->attributes.erase("\\abc9_box_seq");
if (abc9_box) {
module->swap_names(cell, existing_cell);
module->remove(existing_cell);
}
RTLIL::Module* box_module = design->module(mapped_cell->type); RTLIL::Module* box_module = design->module(mapped_cell->type);
auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop"); auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
for (auto &conn : mapped_cell->connections()) { for (auto &mapped_conn : mapped_cell->connections()) {
// Skip entire box ports composed entirely of padding only
if (abc9_box && conn.second.is_wire() && conn.second.as_wire()->get_bool_attribute(ID(abc9_padding)))
continue;
RTLIL::SigSpec newsig; RTLIL::SigSpec newsig;
for (auto c : conn.second.chunks()) { for (auto c : mapped_conn.second.chunks()) {
if (c.width == 0) if (c.width == 0)
continue; continue;
//log_assert(c.width == 1); //log_assert(c.width == 1);
@ -465,19 +447,40 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
c.wire = module->wires_.at(remap_name(c.wire->name)); c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c); newsig.append(c);
} }
cell->setPort(conn.first, newsig); if (existing_cell) {
auto it = existing_cell->connections_.find(mapped_conn.first);
if (!abc9_flop) { if (it == existing_cell->connections_.end())
if (cell->input(conn.first)) { continue;
for (auto i : newsig) log_assert(GetSize(newsig) >= GetSize(it->second));
bit2sinks[i].push_back(cell); newsig = newsig.extract(0, GetSize(it->second));
for (auto i : conn.second)
bit_users[i].insert(mapped_cell->name);
}
if (cell->output(conn.first))
for (auto i : conn.second)
bit_drivers[i].insert(mapped_cell->name);
} }
cell->setPort(mapped_conn.first, newsig);
if (abc9_flop)
continue;
if (cell->input(mapped_conn.first)) {
for (auto i : newsig)
bit2sinks[i].push_back(cell);
for (auto i : mapped_conn.second)
bit_users[i].insert(mapped_cell->name);
}
if (cell->output(mapped_conn.first))
for (auto i : mapped_conn.second)
bit_drivers[i].insert(mapped_cell->name);
}
if (existing_cell) {
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
if (cell->attributes.erase("\\abc9_box_seq")) {
module->swap_names(cell, existing_cell);
module->remove(existing_cell);
}
}
else {
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
} }
} }