mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings

Browse source 
tests: reduce test warnings
This commit is contained in:
Eddie Hung 2020-06-03 08:37:07 -07:00 • committed by GitHub
commit 46ed0db2ec
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
6 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/xilinx/pmgen_xilinx_srl.ys
View file

@ -1,6 +1,6 @@
read_verilog -icells <<EOT read_verilog -icells <<EOT
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO); module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
parameter DEPTH = 1; parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = 0; parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1; parameter CLKPOL = 1;
parameter ENPOL = 2; parameter ENPOL = 2;

2
tests/arch/xilinx/xilinx_srl.v
View file

@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1; parameter CLKPOL = 1;
parameter ENPOL = 1; parameter ENPOL = 1;
parameter DEPTH = 1; parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT; reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL; wire clk = C ^ CLKPOL;

2
tests/various/attrib07_func_call.v
View file

@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
input wire rst; input wire rst;
input wire [7:0] inp_a; input wire [7:0] inp_a;
input wire [7:0] inp_b; input wire [7:0] inp_b;
output wire [7:0] out; output reg [7:0] out;
always @(posedge clk) always @(posedge clk)
if (rst) out <= 0; if (rst) out <= 0;

2
tests/various/constmsk_testmap.v
View file

@ -1,7 +1,7 @@
(* techmap_celltype = "$reduce_or" *) (* techmap_celltype = "$reduce_or" *)
module my_opt_reduce_or(...); module my_opt_reduce_or(...);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 2;
parameter Y_WIDTH = 1; parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A; input [A_WIDTH-1:0] A;

4
tests/various/shregmap.v
View file

@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
endmodule endmodule
module $__SHREG_DFF_P_(input C, D, output Q); module $__SHREG_DFF_P_(input C, D, output Q);
parameter DEPTH = 1; parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT; reg [DEPTH-1:0] r = INIT;
always @(posedge C) always @(posedge C)
@ -38,7 +38,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q); module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1; parameter CLKPOL = 1;
parameter ENPOL = 1; parameter ENPOL = 1;
parameter DEPTH = 1; parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT; reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL; wire clk = C ^ CLKPOL;

2
tests/verilog/bug2042-sv.ys
View file

@ -2,7 +2,7 @@ read_verilog -sv <<EOT
module Task_Test_Top module Task_Test_Top
( (
input a, input a,
output b output reg b
); );
task SomeTaskName(a); task SomeTaskName(a);