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Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings

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tests: reduce test warnings
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Eddie Hung 2020-06-03 08:37:07 -07:00 • committed by GitHub
commit 46ed0db2ec
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6 changed files with 7 additions and 7 deletions
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2
tests/arch/xilinx/pmgen_xilinx_srl.ys
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@ -1,6 +1,6 @@
read_verilog -icells <<EOT
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
parameter DEPTH = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;

2
tests/arch/xilinx/xilinx_srl.v
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@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;