mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-01 07:40:42 +00:00
Code Activity

hierarchy - proc reorder

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-18 09:06:43 +02:00
parent 03a3deec43
commit 46af9a0ff7
4 changed files with 10 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/anlogic/dffs.ys
View file

@ -1,8 +1,8 @@
read_verilog dffs.v
design -save read
proc
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
proc
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module