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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-10-14 11:21:54 -07:00 • committed by GitHub
commit 469f5a707a
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92 changed files with 970 additions and 652 deletions
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4
passes/pmgen/microchip_dsp.cc
View file

@ -128,7 +128,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -244,7 +244,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};

10
passes/pmgen/xilinx_dsp.cc
View file

@ -339,11 +339,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.overflow->type == ID($ge)) {
Const B = st.overflow->getPort(ID::B).as_const();
log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
// that one hi bit
for (auto &b : B.bits)
for (auto &b : B.bits())
if (b == State::S0) b = State::S1;
else if (b == State::S1) {
b = State::S0;
@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -579,7 +579,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -702,7 +702,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};

2
passes/pmgen/xilinx_dsp.pmg
View file

@ -363,7 +363,7 @@ match overflow
select GetSize(port(overflow, \Y)) <= 48
select port(overflow, \B).is_fully_const()
define <Const> B port(overflow, \B).as_const()
select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1
select std::count(B.begin(), B.end(), State::S1) == 1
index <SigSpec> port(overflow, \A) === sigP
optional
endmatch

4
passes/pmgen/xilinx_srl.cc
View file

@ -40,7 +40,7 @@ void run_fixed(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
}
@ -121,7 +121,7 @@ void run_variable(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
}