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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-10-14 11:21:54 -07:00 • committed by GitHub
commit 469f5a707a
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92 changed files with 970 additions and 652 deletions
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4
passes/hierarchy/hierarchy.cc
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@ -219,7 +219,7 @@ struct IFExpander
const RTLIL::SigSpec &conn_signals)
{
// Check if the connected wire is a potential interface in the parent module
std::string interface_name_str = conn_signals.bits()[0].wire->name.str();
std::string interface_name_str = conn_signals[0].wire->name.str();
// Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
interface_name_str.replace(0,23,"");
interface_name_str = "\\" + interface_name_str;
@ -289,7 +289,7 @@ struct IFExpander
return;
// If the connection looks like an interface, handle it.
const auto &bits = conn_signals.bits();
const auto &bits = conn_signals;
if (bits.size() == 1 && bits[0].wire->get_bool_attribute(ID::is_interface))
on_interface(submodule, conn_name, conn_signals);
}