From ae14b5e6a85c5f66f6a5b7efd2257e3388473c68 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 3 Aug 2026 14:55:03 +0200
Subject: [PATCH 1/2] hierarchy: fix cache usage by caching false too

---
 passes/hierarchy/hierarchy.cc | 34 ++++++++++++++++++++--------------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 08b14dca0..dceda1624 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -684,24 +684,30 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 
 bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 {
-	if (cache.count(mod) == 0)
-		for (auto c : mod->cells()) {
-			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
-				return cache[mod] = true;
-		}
-	return cache[mod];
+	auto it = cache.find(mod);
+	if (it != cache.end())
+		return it->second;
+	cache[mod] = false;
+	for (auto c : mod->cells()) {
+		RTLIL::Module *m = mod->design->module(c->type);
+		if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
+			return cache[mod] = true;
+	}
+	return false;
 }
 
 bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 {
-	if (cache.count(mod) == 0)
-		for (auto c : mod->cells()) {
-			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
-				return cache[mod] = true;
-		}
-	return cache[mod];
+	auto it = cache.find(mod);
+	if (it != cache.end())
+		return it->second;
+	cache[mod] = false;
+	for (auto c : mod->cells()) {
+		RTLIL::Module *m = mod->design->module(c->type);
+		if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+			return cache[mod] = true;
+	}
+	return false;
 }
 
 int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)

From a27378cff8404ed46d2cc2177b8d6a52e86cbf1e Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 3 Aug 2026 15:55:22 +0200
Subject: [PATCH 2/2] hierarchy: regression test for keep cache

---
 tests/various/hierarchy_recursive.v  |  3 +++
 tests/various/hierarchy_recursive.ys | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 tests/various/hierarchy_recursive.v
 create mode 100644 tests/various/hierarchy_recursive.ys

diff --git a/tests/various/hierarchy_recursive.v b/tests/various/hierarchy_recursive.v
new file mode 100644
index 000000000..9d4fd323c
--- /dev/null
+++ b/tests/various/hierarchy_recursive.v
@@ -0,0 +1,3 @@
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+endmodule
\ No newline at end of file
diff --git a/tests/various/hierarchy_recursive.ys b/tests/various/hierarchy_recursive.ys
new file mode 100644
index 000000000..e9f203828
--- /dev/null
+++ b/tests/various/hierarchy_recursive.ys
@@ -0,0 +1,25 @@
+read_verilog hierarchy_recursive.v
+hierarchy -auto-top
+select -assert-any top
+select -assert-none a:keep
+
+design -reset
+read_verilog <<EOT
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+always @(x) $display("x=%d", x);
+endmodule
+EOT
+hierarchy -auto-top
+select -assert-any top %% a:keep
+
+design -reset
+read_verilog -formal <<EOT
+module a(input x); b b_i(.x(x)); endmodule
+module b(input x); a a_i(.x(x)); always @(x) assert (x == x); endmodule
+module top(input x); a a_i(.x(x)); endmodule
+EOT
+hierarchy -top top
+select -assert-any a %% a:keep
+select -assert-any b %% a:keep
+select -assert-any top %% a:keep