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Docs: Move rtlil_text (back) to appendix
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Krystine Sherwin
parent
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5 changed files with 56 additions and 62 deletions
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Internal formats
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================
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.. todo:: brief overview for the internal formats index
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Yosys uses two different internal formats. The first is used to store an
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abstract syntax tree (AST) of a Verilog input file. This format is simply called
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AST and is generated by the Verilog Frontend. This data structure is consumed by
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a subsystem called AST Frontend [1]_. This AST Frontend then generates a design
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in Yosys' main internal format, the
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Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does
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that by first performing a number of simplifications within the AST
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representation and then generating RTLIL from the simplified AST data structure.
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The RTLIL representation is used by all passes as input and outputs. This has
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the following advantages over using different representational formats between
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different passes:
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- The passes can be rearranged in a different order and passes can be removed
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or inserted.
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- Passes can simply pass-thru the parts of the design they don't change without
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the need to convert between formats. In fact Yosys passes output the same
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data structure they received as input and performs all changes in place.
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- All passes use the same interface, thus reducing the effort required to
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understand a pass when reading the Yosys source code, e.g. when adding
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additional features.
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The RTLIL representation is basically a netlist representation with the
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following additional features:
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- An internal cell library with fixed-function cells to represent RTL datapath
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and register cells as well as logical gate-level cells (single-bit gates and
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registers).
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- Support for multi-bit values that can use individual bits from wires as well
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as constant bits to represent coarse-grain netlists.
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- Support for basic behavioural constructs (if-then-else structures and
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multi-case switches with a sensitivity list for updating the outputs).
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- Support for multi-port memories.
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The use of RTLIL also has the disadvantage of having a very powerful format
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between all passes, even when doing gate-level synthesis where the more advanced
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features are not needed. In order to reduce complexity for passes that operate
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on a low-level representation, these passes check the features used in the input
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RTLIL and fail to run when unsupported high-level constructs are used. In such
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cases a pass that transforms the higher-level constructs to lower-level
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constructs must be called from the synthesis script first.
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.. toctree::
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:maxdepth: 3
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:maxdepth: 3
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overview
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rtlil_rep
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rtlil_text
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cell_library
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rtlil_rep
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.. [1]
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In Yosys the term pass is only used to refer to commands that operate on the
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RTLIL data structure.
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@ -1,53 +0,0 @@
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Format overview
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===============
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Yosys uses two different internal formats. The first is used to store an
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abstract syntax tree (AST) of a Verilog input file. This format is simply called
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AST and is generated by the Verilog Frontend. This data structure is consumed by
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a subsystem called AST Frontend [1]_. This AST Frontend then generates a design
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in Yosys' main internal format, the
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Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does
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that by first performing a number of simplifications within the AST
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representation and then generating RTLIL from the simplified AST data structure.
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The RTLIL representation is used by all passes as input and outputs. This has
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the following advantages over using different representational formats between
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different passes:
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- The passes can be rearranged in a different order and passes can be removed
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or inserted.
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- Passes can simply pass-thru the parts of the design they don't change without
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the need to convert between formats. In fact Yosys passes output the same
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data structure they received as input and performs all changes in place.
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- All passes use the same interface, thus reducing the effort required to
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understand a pass when reading the Yosys source code, e.g. when adding
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additional features.
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The RTLIL representation is basically a netlist representation with the
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following additional features:
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- An internal cell library with fixed-function cells to represent RTL datapath
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and register cells as well as logical gate-level cells (single-bit gates and
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registers).
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- Support for multi-bit values that can use individual bits from wires as well
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as constant bits to represent coarse-grain netlists.
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- Support for basic behavioural constructs (if-then-else structures and
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multi-case switches with a sensitivity list for updating the outputs).
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- Support for multi-port memories.
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The use of RTLIL also has the disadvantage of having a very powerful format
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between all passes, even when doing gate-level synthesis where the more advanced
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features are not needed. In order to reduce complexity for passes that operate
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on a low-level representation, these passes check the features used in the input
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RTLIL and fail to run when unsupported high-level constructs are used. In such
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cases a pass that transforms the higher-level constructs to lower-level
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constructs must be called from the synthesis script first.
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.. [1]
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In Yosys the term pass is only used to refer to commands that operate on the
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RTLIL data structure.
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@ -1,297 +0,0 @@
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.. _chapter:textrtlil:
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RTLIL text representation
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-------------------------
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This appendix documents the text representation of RTLIL in extended Backus-Naur
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form (EBNF).
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The grammar is not meant to represent semantic limitations. That is, the grammar
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is "permissive", and later stages of processing perform more rigorous checks.
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The grammar is also not meant to represent the exact grammar used in the RTLIL
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frontend, since that grammar is specific to processing by lex and yacc, is even
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more permissive, and is somewhat less understandable than simple EBNF notation.
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Finally, note that all statements (rules ending in ``-stmt``) terminate in an
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end-of-line. Because of this, a statement cannot be broken into multiple lines.
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Lexical elements
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~~~~~~~~~~~~~~~~
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Characters
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^^^^^^^^^^
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An RTLIL file is a stream of bytes. Strictly speaking, a "character" in an RTLIL
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file is a single byte. The lexer treats multi-byte encoded characters as
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consecutive single-byte characters. While other encodings *may* work, UTF-8 is
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known to be safe to use. Byte order marks at the beginning of the file will
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cause an error.
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ASCII spaces (32) and tabs (9) separate lexer tokens.
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A ``nonws`` character, used in identifiers, is any character whose encoding
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consists solely of bytes above ASCII space (32).
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An ``eol`` is one or more consecutive ASCII newlines (10) and carriage returns
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(13).
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Identifiers
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^^^^^^^^^^^
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There are two types of identifiers in RTLIL:
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- Publically visible identifiers
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- Auto-generated identifiers
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.. code:: BNF
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<id> ::= <public-id> | <autogen-id>
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<public-id> ::= \ <nonws>+
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<autogen-id> ::= $ <nonws>+
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Values
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^^^^^^
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A *value* consists of a width in bits and a bit representation, most
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significant bit first. Bits may be any of:
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- ``0``: A logic zero value
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- ``1``: A logic one value
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- ``x``: An unknown logic value (or don't care in case patterns)
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- ``z``: A high-impedance value (or don't care in case patterns)
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- ``m``: A marked bit (internal use only)
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- ``-``: A don't care value
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An *integer* is simply a signed integer value in decimal format. **Warning:**
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Integer constants are limited to 32 bits. That is, they may only be in the range
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:math:`[-2147483648, 2147483648)`. Integers outside this range will result in an
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error.
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.. code:: BNF
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<value> ::= <decimal-digit>+ ' <binary-digit>*
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<decimal-digit> ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
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<binary-digit> ::= 0 | 1 | x | z | m | -
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<integer> ::= -? <decimal-digit>+
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Strings
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^^^^^^^
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A string is a series of characters delimited by double-quote characters. Within
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a string, any character except ASCII NUL (0) may be used. In addition, certain
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escapes can be used:
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- ``\n``: A newline
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- ``\t``: A tab
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- ``\ooo``: A character specified as a one, two, or three digit octal value
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All other characters may be escaped by a backslash, and become the following
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character. Thus:
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- ``\\``: A backslash
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- ``\"``: A double-quote
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- ``\r``: An 'r' character
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Comments
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^^^^^^^^
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A comment starts with a ``#`` character and proceeds to the end of the line. All
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comments are ignored.
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File
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~~~~
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A file consists of an optional autoindex statement followed by zero or more
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modules.
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.. code:: BNF
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<file> ::= <autoidx-stmt>? <module>*
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Autoindex statements
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^^^^^^^^^^^^^^^^^^^^
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The autoindex statement sets the global autoindex value used by Yosys when it
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needs to generate a unique name, e.g. ``flattenN``. The N part is filled with
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the value of the global autoindex value, which is subsequently incremented. This
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global has to be dumped into RTLIL, otherwise e.g. dumping and running a pass
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would have different properties than just running a pass on a warm design.
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.. code:: BNF
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<autoidx-stmt> ::= autoidx <integer> <eol>
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Modules
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^^^^^^^
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Declares a module, with zero or more attributes, consisting of zero or more
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wires, memories, cells, processes, and connections.
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.. code:: BNF
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<module> ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
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<module-stmt> ::= module <id> <eol>
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<module-body> ::= (<param-stmt>
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| <wire>
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| <memory>
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| <cell>
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| <process>)*
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<param-stmt> ::= parameter <id> <constant>? <eol>
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<constant> ::= <value> | <integer> | <string>
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<module-end-stmt> ::= end <eol>
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Attribute statements
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^^^^^^^^^^^^^^^^^^^^
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Declares an attribute with the given identifier and value.
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.. code:: BNF
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<attr-stmt> ::= attribute <id> <constant> <eol>
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Signal specifications
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^^^^^^^^^^^^^^^^^^^^^
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A signal is anything that can be applied to a cell port, i.e. a constant value,
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all bits or a selection of bits from a wire, or concatenations of those.
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**Warning:** When an integer constant is a sigspec, it is always 32 bits wide,
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2's complement. For example, a constant of :math:`-1` is the same as
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``32'11111111111111111111111111111111``, while a constant of :math:`1` is the
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same as ``32'1``.
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See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
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.. code:: BNF
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<sigspec> ::= <constant>
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| <wire-id>
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| <sigspec> [ <integer> (:<integer>)? ]
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| { <sigspec>* }
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Connections
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^^^^^^^^^^^
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Declares a connection between the given signals.
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.. code:: BNF
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<conn-stmt> ::= connect <sigspec> <sigspec> <eol>
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Wires
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^^^^^
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Declares a wire, with zero or more attributes, with the given identifier and
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options in the enclosing module.
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See :ref:`sec:rtlil_cell_wire` for an overview of wires.
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.. code:: BNF
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<wire> ::= <attr-stmt>* <wire-stmt>
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<wire-stmt> ::= wire <wire-option>* <wire-id> <eol>
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<wire-id> ::= <id>
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<wire-option> ::= width <integer>
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| offset <integer>
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| input <integer>
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| output <integer>
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| inout <integer>
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| upto
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| signed
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Memories
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^^^^^^^^
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Declares a memory, with zero or more attributes, with the given identifier and
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options in the enclosing module.
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See :ref:`sec:rtlil_memory` for an overview of memory cells, and
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:ref:`sec:memcells` for details about memory cell types.
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.. code:: BNF
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<memory> ::= <attr-stmt>* <memory-stmt>
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<memory-stmt> ::= memory <memory-option>* <id> <eol>
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<memory-option> ::= width <integer>
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| size <integer>
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| offset <integer>
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Cells
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^^^^^
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Declares a cell, with zero or more attributes, with the given identifier and
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type in the enclosing module.
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Cells perform functions on input signals. See
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:doc:`/yosys_internals/formats/cell_library` for a detailed list of cell types.
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.. code:: BNF
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<cell> ::= <attr-stmt>* <cell-stmt> <cell-body-stmt>* <cell-end-stmt>
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<cell-stmt> ::= cell <cell-type> <cell-id> <eol>
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<cell-id> ::= <id>
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<cell-type> ::= <id>
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<cell-body-stmt> ::= parameter (signed | real)? <id> <constant> <eol>
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| connect <id> <sigspec> <eol>
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<cell-end-stmt> ::= end <eol>
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Processes
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^^^^^^^^^
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Declares a process, with zero or more attributes, with the given identifier in
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the enclosing module. The body of a process consists of zero or more
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assignments, exactly one switch, and zero or more syncs.
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See :ref:`sec:rtlil_process` for an overview of processes.
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.. code:: BNF
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<process> ::= <attr-stmt>* <proc-stmt> <process-body> <proc-end-stmt>
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<proc-stmt> ::= process <id> <eol>
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<process-body> ::= <assign-stmt>* <switch>? <assign-stmt>* <sync>*
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<assign-stmt> ::= assign <dest-sigspec> <src-sigspec> <eol>
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<dest-sigspec> ::= <sigspec>
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<src-sigspec> ::= <sigspec>
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<proc-end-stmt> ::= end <eol>
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Switches
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^^^^^^^^
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Switches test a signal for equality against a list of cases. Each case specifies
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a comma-separated list of signals to check against. If there are no signals in
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the list, then the case is the default case. The body of a case consists of zero
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or more switches and assignments. Both switches and cases may have zero or more
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attributes.
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.. code:: BNF
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<switch> ::= <switch-stmt> <case>* <switch-end-stmt>
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<switch-stmt> := <attr-stmt>* switch <sigspec> <eol>
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<case> ::= <attr-stmt>* <case-stmt> <case-body>
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<case-stmt> ::= case <compare>? <eol>
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<compare> ::= <sigspec> (, <sigspec>)*
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<case-body> ::= (<switch> | <assign-stmt>)*
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<switch-end-stmt> ::= end <eol>
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Syncs
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^^^^^
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Syncs update signals with other signals when an event happens. Such an event may
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be:
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- An edge or level on a signal
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- Global clock ticks
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- Initialization
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- Always
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.. code:: BNF
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<sync> ::= <sync-stmt> <update-stmt>*
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<sync-stmt> ::= sync <sync-type> <sigspec> <eol>
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| sync global <eol>
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| sync init <eol>
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| sync always <eol>
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<sync-type> ::= low | high | posedge | negedge | edge
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<update-stmt> ::= update <dest-sigspec> <src-sigspec> <eol>
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