mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

ABC9 to understand flops

Browse source
This commit is contained in:
Eddie Hung 2019-05-31 15:23:33 -07:00
parent eb08e71bd1
commit 4623177655
1 changed files with 27 additions and 46 deletions
Download patch file Download diff file Expand all files Collapse all files

73
backends/aiger/xaiger.cc
View file

@ -181,7 +181,6 @@ struct XAigerWriter
for (auto cell : module->cells())
{
RTLIL::Module* inst_module = module->design->module(cell->type);
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
bool known_type = yosys_celltypes.cell_known(cell->type);
if (!holes_mode) {
@ -258,22 +257,28 @@ struct XAigerWriter
// continue;
//}
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
if (inst_flop) {
SigBit d, q;
for (const auto &c : cell->connections()) {
auto is_input = cell->input(c.first);
auto is_output = cell->output(c.first);
log_assert(is_input || is_output);
RTLIL::Wire* port = inst_module->wire(c.first);
for (auto b : c.second.bits()) {
auto is_input = cell->input(c.first);
auto is_output = cell->output(c.first);
log_assert(is_input || is_output);
if (is_input && inst_module->wire(c.first)->attributes.count("\\abc_flop_d")) {
SigBit I = sigmap(b);
if (I != b)
alias_map[b] = I;
if (is_input && port->attributes.count("\\abc_flop_d")) {
d = b;
SigBit I = sigmap(d);
if (I != d)
alias_map[I] = d;
unused_bits.erase(d);
}
if (is_output && inst_module->wire(c.first)->attributes.count("\\abc_flop_q")) {
SigBit O = sigmap(b);
q = O;
if (is_output && port->attributes.count("\\abc_flop_q")) {
q = b;
SigBit O = sigmap(q);
if (O != q)
alias_map[O] = q;
undriven_bits.erase(O);
}
}
}
@ -281,7 +286,6 @@ struct XAigerWriter
abc_box_seen = inst_module->attributes.count("\\abc_box_id");
ff_bits.emplace_back(d, q);
undriven_bits.erase(q);
}
else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
abc_box_seen = true;
@ -507,8 +511,9 @@ struct XAigerWriter
}
for (auto &f : ff_bits) {
auto bit = f.second;
RTLIL::SigBit bit = f.second;
aig_m++, aig_i++;
log_assert(!aig_map.count(bit));
aig_map[bit] = 2*aig_m;
}
@ -516,12 +521,9 @@ struct XAigerWriter
for (auto &c : ci_bits) {
RTLIL::SigBit bit = std::get<0>(c);
aig_m++, aig_i++;
log_assert(!aig_map.count(bit));
aig_map[bit] = 2*aig_m;
//auto r = aig_map.insert(std::make_pair(c.first, c.second));
//if (!r.second) {
// ff_aig_map[std::get<0>(c)] = 2*aig_m;
//}
auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
if (!r.second)
ff_aig_map[bit] = 2*aig_m;
}
if (imode && input_bits.empty()) {
@ -597,7 +599,8 @@ struct XAigerWriter
for (auto &f : ff_bits) {
aig_o++;
aig_outputs.push_back(ff_aig_map.at(f.second));
RTLIL::SigBit bit = f.second;
aig_outputs.push_back(ff_aig_map.at(bit));
}
if (omode && output_bits.empty()) {
@ -778,8 +781,8 @@ struct XAigerWriter
write_h_buffer(num_outputs + ff_bits.size()+ co_bits.size());
log_debug("piNum = %zu\n", input_bits.size() + ff_bits.size());
write_h_buffer(input_bits.size()+ ff_bits.size());
log_debug("poNum = %d\n", num_outputs);
write_h_buffer(num_outputs);
log_debug("poNum = %zu\n", num_outputs + ff_bits.size());
write_h_buffer(num_outputs + ff_bits.size());
log_debug("boxNum = %zu\n", box_list.size());
write_h_buffer(box_list.size());
@ -856,7 +859,7 @@ struct XAigerWriter
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
if (!ff_bits.empty()) {
/*if (!ff_bits.empty())*/ {
std::stringstream r_buffer;
auto write_r_buffer = [&r_buffer](int i32) {
// TODO: Don't assume we're on little endian
@ -867,6 +870,7 @@ struct XAigerWriter
#endif
r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
};
log_debug("flopNum = %zu\n", ff_bits.size());
write_r_buffer(ff_bits.size());
int mergeability_class = 1;
for (auto cell : ff_bits)
@ -923,29 +927,6 @@ struct XAigerWriter
f.write(buffer_str.data(), buffer_str.size());
holes_module->design->remove(holes_module);
}
std::stringstream r_buffer;
auto write_r_buffer = [&r_buffer](int i32) {
// TODO: Don't assume we're on little endian
#ifdef _WIN32
int i32_be = _byteswap_ulong(i32);
#else
int i32_be = __builtin_bswap32(i32);
#endif
r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
};
write_r_buffer(0);
f << "r";
buffer_str = r_buffer.str();
// TODO: Don't assume we're on little endian
#ifdef _WIN32
buffer_size_be = _byteswap_ulong(buffer_str.size());
#else
buffer_size_be = __builtin_bswap32(buffer_str.size());
#endif
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
}
f << stringf("Generated by %s\n", yosys_version_str);