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	Fixed handling of [a-fxz?] in decimal constants
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					 2 changed files with 11 additions and 2 deletions
				
			
		|  | @ -48,7 +48,9 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits) | ||||||
| { | { | ||||||
| 	int carry = 0; | 	int carry = 0; | ||||||
| 	for (size_t i = 0; i < digits.size(); i++) { | 	for (size_t i = 0; i < digits.size(); i++) { | ||||||
| 		log_assert(digits[i] < 10); | 		if (digits[i] >= 10) | ||||||
|  | 			log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n", | ||||||
|  | 				current_filename.c_str(), get_line_num()); | ||||||
| 		digits[i] += carry * 10; | 		digits[i] += carry * 10; | ||||||
| 		carry = digits[i] % 2; | 		carry = digits[i] % 2; | ||||||
| 		digits[i] /= 2; | 		digits[i] /= 2; | ||||||
|  | @ -91,6 +93,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le | ||||||
| 		str++; | 		str++; | ||||||
| 	} | 	} | ||||||
| 
 | 
 | ||||||
|  | 	if (base == 10 && GetSize(digits) == 1 && digits.front() >= 0xf0) | ||||||
|  | 		base = 2; | ||||||
|  | 
 | ||||||
| 	if (base == 10) { | 	if (base == 10) { | ||||||
| 		data.clear(); | 		data.clear(); | ||||||
| 		if (len_in_bits < 0) { | 		if (len_in_bits < 0) { | ||||||
|  | @ -138,7 +143,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn | ||||||
| 		AstNode *ret = const2ast(code, case_type); | 		AstNode *ret = const2ast(code, case_type); | ||||||
| 		if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) | 		if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) | ||||||
| 			log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n", | 			log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n", | ||||||
| 				current_filename.c_str(), frontend_verilog_yyget_lineno()); | 				current_filename.c_str(), get_line_num()); | ||||||
| 		return ret; | 		return ret; | ||||||
| 	} | 	} | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -3280,6 +3280,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri | ||||||
| { | { | ||||||
| 	cover("kernel.rtlil.sigspec.parse"); | 	cover("kernel.rtlil.sigspec.parse"); | ||||||
| 
 | 
 | ||||||
|  | 	AST::current_filename = "input"; | ||||||
|  | 	AST::use_internal_line_num(); | ||||||
|  | 	AST::set_line_num(0); | ||||||
|  | 
 | ||||||
| 	std::vector<std::string> tokens; | 	std::vector<std::string> tokens; | ||||||
| 	sigspec_parse_split(tokens, str, ','); | 	sigspec_parse_split(tokens, str, ','); | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
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