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read_verilog: copy inout ports in and out of functions/tasks

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George Rennie 2025-05-31 01:08:15 +01:00
parent 4f7ea38b49
commit 45e8ff476e
1 changed files with 14 additions and 6 deletions
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20
frontends/ast/simplify.cc
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@ -4099,16 +4099,24 @@ skip_dynamic_range_lvalue_expansion:;
delete arg; delete arg;
continue; continue;
} }
AstNode *wire_id = new AstNode(AST_IDENTIFIER); AstNode *wire_id = new AstNode(AST_IDENTIFIER);
wire_id->str = wire->str; wire_id->str = wire->str;
AstNode *assign = child->is_input ?
new AstNode(AST_ASSIGN_EQ, wire_id, arg) : if (child->is_input) {
new AstNode(AST_ASSIGN_EQ, arg, wire_id); AstNode *assign = new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
assign->children[0]->was_checked = true; assign->children[0]->was_checked = true;
if (child->is_input)
new_stmts.push_back(assign); new_stmts.push_back(assign);
else }
if (child->is_output) {
AstNode *assign = new AstNode(AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
assign->children[0]->was_checked = true;
output_assignments.push_back(assign); output_assignments.push_back(assign);
}
delete arg;
delete wire_id;
} }
} }