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	Add "check -mapped"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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					 2 changed files with 36 additions and 21 deletions
				
			
		|  | @ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev | |||
|     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) | ||||
|     - "synth_ice40 -dsp" to infer DSP blocks | ||||
|     - Added latch support to synth_xilinx | ||||
|     - Added "check -mapped" | ||||
| 
 | ||||
| Yosys 0.8 .. Yosys 0.9 | ||||
| ---------------------- | ||||
|  |  | |||
|  | @ -47,6 +47,9 @@ struct CheckPass : public Pass { | |||
| 		log("When called with -initdrv then this command also checks for wires which have\n"); | ||||
| 		log("the 'init' attribute set and aren't driven by a FF cell type.\n"); | ||||
| 		log("\n"); | ||||
| 		log("When called with -mapped then this command also checks for internal cells\n"); | ||||
| 		log("that have not been mapped to cells of the target architecture.\n"); | ||||
| 		log("\n"); | ||||
| 		log("When called with -assert then the command will produce an error if any\n"); | ||||
| 		log("problems are found in the current design.\n"); | ||||
| 		log("\n"); | ||||
|  | @ -56,6 +59,7 @@ struct CheckPass : public Pass { | |||
| 		int counter = 0; | ||||
| 		bool noinit = false; | ||||
| 		bool initdrv = false; | ||||
| 		bool mapped = false; | ||||
| 		bool assert_mode = false; | ||||
| 
 | ||||
| 		size_t argidx; | ||||
|  | @ -68,6 +72,10 @@ struct CheckPass : public Pass { | |||
| 				initdrv = true; | ||||
| 				continue; | ||||
| 			} | ||||
| 			if (args[argidx] == "-mapped") { | ||||
| 				mapped = true; | ||||
| 				continue; | ||||
| 			} | ||||
| 			if (args[argidx] == "-assert") { | ||||
| 				assert_mode = true; | ||||
| 				continue; | ||||
|  | @ -135,6 +143,11 @@ struct CheckPass : public Pass { | |||
| 			TopoSort<string> topo; | ||||
| 
 | ||||
| 			for (auto cell : module->cells()) | ||||
| 			{ | ||||
| 				if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { | ||||
| 					log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type)); | ||||
| 					counter++; | ||||
| 				} | ||||
| 				for (auto &conn : cell->connections()) { | ||||
| 					SigSpec sig = sigmap(conn.second); | ||||
| 					bool logic_cell = yosys_celltypes.cell_evaluable(cell->type); | ||||
|  | @ -159,6 +172,7 @@ struct CheckPass : public Pass { | |||
| 						for (auto bit : sig) | ||||
| 							if (bit.wire) wire_drivers_count[bit]++; | ||||
| 				} | ||||
| 			} | ||||
| 
 | ||||
| 			pool<SigBit> init_bits; | ||||
| 
 | ||||
|  |  | |||
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