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Add shregmap -tech xilinx test

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This commit is contained in:
Eddie Hung 2019-06-12 08:34:06 -07:00
parent 6cdea93724
commit 45c2a5f876
2 changed files with 63 additions and 2 deletions
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37
tests/various/shregmap.ys
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@ -1,6 +1,8 @@
read_verilog shregmap.v
design -save read
design -copy-to model $__SHREG_DFF_P_
hierarchy -top shregmap_test
hierarchy -top shregmap_static_test
prep
design -save gold
@ -29,3 +31,36 @@ stat
design -load gate
stat
##########
design -load read
design -copy-to model $__XILINX_SHREG_
hierarchy -top shregmap_variable_test
prep
design -save gold
simplemap t:$dff t:$dffe
shregmap -tech xilinx
stat
# show -width
write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat