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Merge pull request #5460 from povik/timeest-comb

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timeest: Add top ports launching/sampling
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Martin Povišer 2025-11-05 14:29:34 +01:00 • committed by GitHub
commit 45bb5c690d
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2 changed files with 52 additions and 15 deletions
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12
tests/various/timeest.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOF
module top(input [3:0] a, input [3:0] b, output [7:0] y);
assign y = a * b;
endmodule
module top2(input [7:0] a, input [7:0] b, output [15:0] y);
assign y = a * b;
endmodule
EOF
synth
timeest