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Support for 'modports' for System Verilog interfaces

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This commit is contained in:
Ruben Undheim 2018-10-12 20:58:37 +02:00
parent 75009ada3c
commit 458a94059e
8 changed files with 121 additions and 14 deletions
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29
frontends/ast/genrtlil.cc
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@ -853,6 +853,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENIF:
case AST_GENCASE:
case AST_PACKAGE:
case AST_MODPORT:
case AST_MODPORTMEMBER:
break;
case AST_INTERFACEPORT: {
// If a port in a module with unknown type is found, mark it as "is_interface=true"
@ -865,6 +867,33 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = true;
wire->port_output = true;
wire->set_bool_attribute("\\is_interface");
if (children.size() > 0) {
for(size_t i=0; i<children.size();i++) {
if(children[i]->type == AST_INTERFACEPORTTYPE) {
std::string name_type = children[i]->str;
size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
if (ndots == 0) {
wire->attributes["\\interface_type"] = name_type;
}
else {
std::stringstream name_type_stream(name_type);
std::string segment;
std::vector<std::string> seglist;
while(std::getline(name_type_stream, segment, '.')) {
seglist.push_back(segment);
}
if (ndots == 1) {
wire->attributes["\\interface_type"] = seglist[0];
wire->attributes["\\interface_modport"] = seglist[1];
}
else {
log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
}
}
break;
}
}
}
wire->upto = 0;
}
break;