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Support for 'modports' for System Verilog interfaces
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75009ada3c
commit
458a94059e
8 changed files with 121 additions and 14 deletions
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@ -1118,7 +1118,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
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}
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// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail)
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{
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AstNode *new_ast = NULL;
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std::string modname = derive_common(design, parameters, &new_ast, mayfail);
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@ -1143,14 +1143,46 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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for(auto &intf : interfaces) {
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RTLIL::Module * intfmodule = intf.second;
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std::string intfname = intf.first.str();
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AstNode *modport = NULL;
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if (modports.count(intfname) > 0) {
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std::string interface_modport = modports.at(intfname).str();
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AstModule *ast_module_of_interface = (AstModule*)intfmodule;
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AstNode *ast_node_of_interface = ast_module_of_interface->ast;
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for (auto &ch : ast_node_of_interface->children) {
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if (ch->type == AST_MODPORT) {
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if (ch->str == interface_modport) {
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modport = ch;
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}
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}
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}
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}
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for (auto &wire_it : intfmodule->wires_){
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
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std::string origname = log_id(wire_it.first);
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std::string newname = intfname + "." + origname;
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wire->str = newname;
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wire->is_input = true;
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wire->is_output = true;
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new_ast->children.push_back(wire);
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if (modport != NULL) {
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bool found_in_modport = false;
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for (auto &ch : modport->children) {
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if (ch->type == AST_MODPORTMEMBER) {
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std::string compare_name = "\\" + origname;
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if (ch->str == compare_name) {
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found_in_modport = true;
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wire->is_input = ch->is_input;
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wire->is_output = ch->is_output;
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break;
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}
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}
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}
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if (found_in_modport) { // If not found in modport, do not create port
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new_ast->children.push_back(wire);
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}
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}
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else { // If no modport, set inout
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wire->is_input = true;
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wire->is_output = true;
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new_ast->children.push_back(wire);
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}
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}
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}
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