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https://github.com/YosysHQ/yosys
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clockgate: add -liberty
This commit is contained in:
Emil J. Tywoniak
parent
a22ff47d62
commit
45880ea7f2
1 changed files with 177 additions and 3 deletions
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@ -1,5 +1,6 @@
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#include "kernel/yosys.h"
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#include "kernel/ff.h"
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#include "libparse.h"
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#include <optional>
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USING_YOSYS_NAMESPACE
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@ -10,6 +11,7 @@ struct ClockGateCell {
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IdString ce_pin;
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IdString clk_in_pin;
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IdString clk_out_pin;
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std::vector<IdString> tie_lo_pins;
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};
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ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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@ -37,6 +39,161 @@ ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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return c;
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}
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static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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find_icgs(std::string filename) {
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std::ifstream f;
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f.open(filename.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", filename.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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auto ast = libparser.ast;
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// We will pick the most suitable ICG absed on tie_lo count and area
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struct ICGRankable {
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ClockGateCell icg;
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double area;
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};
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std::optional<ICGRankable> best_pos;
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std::optional<ICGRankable> best_neg;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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// This is a lot of boilerplate, isn't it?
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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// TODO Should we have user-specified dont_use_cells here?
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const LibertyAst *icg_kind_ast = cell->find("clock_gating_integrated_cell");
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if (icg_kind_ast == nullptr)
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continue;
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auto cell_name = cell->args[0];
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auto icg_kind = icg_kind_ast->value;
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std::vector<std::string> kind_tags;
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std::stringstream ss(icg_kind);
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std::string tag;
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while (std::getline(ss, tag, '_')) {
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kind_tags.push_back(tag);
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}
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if ((kind_tags.size() < 2) || (kind_tags.size() > 4))
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log_error("Malformed liberty file - invalid clock_gating_integrated_cell value %s in cell %s\n",
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icg_kind.c_str(), cell_name.c_str());
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auto internal = kind_tags[0];
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if (internal != "latch") {
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// TODO Is this expected behavior?
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log_warning("Skipping ICG cell %s - not latch-based\n", cell_name.c_str());
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continue;
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}
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auto clk_pol_tag = kind_tags[1];
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bool clk_pol;
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if (clk_pol_tag == "posedge") {
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clk_pol = true;
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} else if (clk_pol_tag == "negedge") {
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clk_pol = false;
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} else {
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log_error("Malformed liberty file - invalid clock_gating_integrated_cell value %s in cell %s\n",
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icg_kind.c_str(), cell_name.c_str());
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continue;
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}
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log_debug("maybe valid icg: %s\n", cell_name.c_str());
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ClockGateCell icg_interface;
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icg_interface.name = RTLIL::escape_id(cell_name);
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for (auto pin : cell->children) {
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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log("Check pin %s\n", pin->args[0].c_str());
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if (auto clk = pin->find("clock_gate_clock_pin")) {
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if (!icg_interface.clk_in_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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cell_name.c_str());
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else
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icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto gclk = pin->find("clock_gate_out_pin")) {
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if (!icg_interface.clk_out_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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cell_name.c_str());
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else
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icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto en = pin->find("clock_gate_enable_pin")) {
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if (!icg_interface.ce_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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cell_name.c_str());
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else
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icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto se = pin->find("clock_gate_test_pin")) {
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icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
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} else {
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const LibertyAst *dir = pin->find("direction");
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if (dir->value == "internal")
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continue;
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log_error("Malformed liberty file - extra pin %s in cell %s\n",
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pin->args[0].c_str(), cell_name.c_str());
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}
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}
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if (icg_interface.clk_in_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
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cell_name.c_str());
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if (icg_interface.clk_out_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_out_pin in cell %s",
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cell_name.c_str());
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if (icg_interface.ce_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
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cell_name.c_str());
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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std::optional<ICGRankable>& icg_to_beat = clk_pol ? best_pos : best_neg;
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bool winning = false;
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if (icg_to_beat) {
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log_debug("ties: %zu ? %zu\n", icg_to_beat->icg.tie_lo_pins.size(),
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icg_interface.tie_lo_pins.size());
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log_debug("area: %f ? %f\n", icg_to_beat->area, area);
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if (icg_to_beat->icg.tie_lo_pins.size() != icg_interface.tie_lo_pins.size())
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winning = icg_to_beat->icg.tie_lo_pins.size() > icg_interface.tie_lo_pins.size();
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else
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winning = icg_to_beat->area > area;
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if (winning)
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log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->icg.name.c_str());
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} else {
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log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
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winning = true;
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}
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if (winning) {
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ICGRankable new_icg {icg_interface, area};
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icg_to_beat.emplace(new_icg);
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}
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}
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std::optional<ClockGateCell> pos;
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std::optional<ClockGateCell> neg;
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if (best_pos) {
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log("Selected rising edge ICG %s\n", best_pos->icg.name.c_str());
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pos.emplace(best_pos->icg);
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}
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if (best_neg) {
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log("Selected falling edge ICG %s\n", best_neg->icg.name.c_str());
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neg.emplace(best_neg->icg);
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}
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return std::make_pair(pos, neg);
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}
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struct ClockgatePass : public Pass {
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ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
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void help() override {
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@ -60,6 +217,7 @@ struct ClockgatePass : public Pass {
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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// TODO -liberty
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log(" -tie_lo <port_name>\n");
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log(" Port <port_name> of the ICG will be tied to zero.\n");
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log(" Intended for DFT scan-enable pins.\n");
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@ -110,8 +268,9 @@ struct ClockgatePass : public Pass {
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::vector<std::string> tie_lo_ports;
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std::vector<std::string> tie_lo_pins;
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int min_net_size = 0;
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std::string liberty_file;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -125,14 +284,29 @@ struct ClockgatePass : public Pass {
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auto rest = args[++argidx];
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neg_icg_desc = icg_from_arg(name, rest);
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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}
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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tie_lo_ports.push_back(RTLIL::escape_id(args[++argidx]));
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tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
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}
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = atoi(args[++argidx].c_str());
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}
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}
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if (!liberty_file.empty())
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std::tie(pos_icg_desc, neg_icg_desc) = find_icgs(liberty_file);
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else {
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for (auto pin : tie_lo_pins) {
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if (pos_icg_desc)
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pos_icg_desc->tie_lo_pins.push_back(pin);
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if (neg_icg_desc)
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neg_icg_desc->tie_lo_pins.push_back(pin);
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}
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}
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extra_args(args, argidx, design);
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pool<Cell*> ce_ffs;
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@ -185,7 +359,7 @@ struct ClockgatePass : public Pass {
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gclk.new_net = module->addWire(NEW_ID);
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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// Tie low DFT ports like scan chain enable
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for (auto port : tie_lo_ports)
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for (auto port : matching_icg_desc->tie_lo_pins)
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icg->setPort(port, Const(0, 1));
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// Fix CE polarity if needed
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if (!clk.pol_ce) {
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