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https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
Renamed SIZE() to GetSize() because of name collision on Win32
This commit is contained in:
Clifford Wolf
parent
c7f5aab625
commit
4569a747f8
48 changed files with 447 additions and 447 deletions
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@ -48,51 +48,51 @@ struct AlumaccWorker
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RTLIL::SigSpec cached_cf, cached_of, cached_sf;
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RTLIL::SigSpec get_lt() {
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if (SIZE(cached_lt) == 0)
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if (GetSize(cached_lt) == 0)
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cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
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return cached_lt;
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}
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RTLIL::SigSpec get_gt() {
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if (SIZE(cached_gt) == 0)
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if (GetSize(cached_gt) == 0)
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cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
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return cached_gt;
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}
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RTLIL::SigSpec get_eq() {
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if (SIZE(cached_eq) == 0)
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if (GetSize(cached_eq) == 0)
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cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
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return cached_eq;
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}
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RTLIL::SigSpec get_ne() {
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if (SIZE(cached_ne) == 0)
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if (GetSize(cached_ne) == 0)
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cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
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return cached_ne;
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}
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RTLIL::SigSpec get_cf() {
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if (SIZE(cached_cf) == 0) {
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if (GetSize(cached_cf) == 0) {
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cached_cf = alu_cell->getPort("\\CO");
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log_assert(SIZE(cached_cf) >= 1);
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[SIZE(cached_cf)-1]);
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log_assert(GetSize(cached_cf) >= 1);
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
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}
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return cached_cf;
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}
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RTLIL::SigSpec get_of() {
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if (SIZE(cached_of) == 0) {
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if (GetSize(cached_of) == 0) {
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cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")};
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log_assert(SIZE(cached_of) >= 2);
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cached_of = alu_cell->module->Xor(NEW_ID, cached_of[SIZE(cached_of)-1], cached_of[SIZE(cached_of)-2]);
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log_assert(GetSize(cached_of) >= 2);
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cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
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}
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return cached_of;
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}
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RTLIL::SigSpec get_sf() {
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if (SIZE(cached_sf) == 0) {
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if (GetSize(cached_sf) == 0) {
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cached_sf = alu_cell->getPort("\\Y");
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cached_sf = cached_sf[SIZE(cached_sf)-1];
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cached_sf = cached_sf[GetSize(cached_sf)-1];
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}
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return cached_sf;
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}
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@ -184,10 +184,10 @@ struct AlumaccWorker
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return true;
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if (!port.is_signed && port.do_subtract)
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return true;
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if (SIZE(port.in_b))
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port_sizes.push_back(SIZE(port.in_a) + SIZE(port.in_b));
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if (GetSize(port.in_b))
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port_sizes.push_back(GetSize(port.in_a) + GetSize(port.in_b));
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else
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port_sizes.push_back(SIZE(port.in_a));
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port_sizes.push_back(GetSize(port.in_a));
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}
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std::sort(port_sizes.begin(), port_sizes.end());
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@ -224,11 +224,11 @@ struct AlumaccWorker
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if (delete_nodes.count(n))
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continue;
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for (int i = 0; i < SIZE(n->macc.ports); i++)
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for (int i = 0; i < GetSize(n->macc.ports); i++)
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{
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auto &port = n->macc.ports[i];
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if (SIZE(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
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if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
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continue;
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auto other_n = sig_macc.at(port.in_a);
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@ -236,13 +236,13 @@ struct AlumaccWorker
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if (other_n->users > 1)
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continue;
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if (SIZE(other_n->y) != SIZE(n->y) && macc_may_overflow(other_n->macc, SIZE(other_n->y), port.is_signed))
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if (GetSize(other_n->y) != GetSize(n->y) && macc_may_overflow(other_n->macc, GetSize(other_n->y), port.is_signed))
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continue;
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log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell));
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bool do_subtract = port.do_subtract;
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for (int j = 0; j < SIZE(other_n->macc.ports); j++) {
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for (int j = 0; j < GetSize(other_n->macc.ports); j++) {
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if (do_subtract)
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other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract;
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if (j == 0)
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@ -278,38 +278,38 @@ struct AlumaccWorker
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alunode_t *alunode;
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for (auto &port : n->macc.ports)
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if (SIZE(port.in_b) > 0) {
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if (GetSize(port.in_b) > 0) {
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goto next_macc;
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} else if (SIZE(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
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} else if (GetSize(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
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C.append(port.in_a);
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} else if (SIZE(A) || port.do_subtract) {
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if (SIZE(B))
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} else if (GetSize(A) || port.do_subtract) {
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if (GetSize(B))
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goto next_macc;
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B = port.in_a;
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b_signed = port.is_signed;
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subtract_b = port.do_subtract;
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} else {
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if (SIZE(A))
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if (GetSize(A))
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goto next_macc;
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A = port.in_a;
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a_signed = port.is_signed;
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}
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if (!a_signed || !b_signed) {
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if (SIZE(A) == SIZE(n->y))
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if (GetSize(A) == GetSize(n->y))
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a_signed = false;
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if (SIZE(B) == SIZE(n->y))
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if (GetSize(B) == GetSize(n->y))
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b_signed = false;
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if (a_signed != b_signed)
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goto next_macc;
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}
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if (SIZE(A) == 0 && SIZE(C) > 0) {
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if (GetSize(A) == 0 && GetSize(C) > 0) {
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A = C[0];
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C.remove(0);
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}
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if (SIZE(B) == 0 && SIZE(C) > 0) {
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if (GetSize(B) == 0 && GetSize(C) > 0) {
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B = C[0];
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C.remove(0);
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}
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@ -317,10 +317,10 @@ struct AlumaccWorker
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if (subtract_b)
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C.append(RTLIL::S1);
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if (SIZE(C) > 1)
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if (GetSize(C) > 1)
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goto next_macc;
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if (!subtract_b && B < A && SIZE(B))
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if (!subtract_b && B < A && GetSize(B))
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std::swap(A, B);
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log(" creating $alu model for $macc %s.\n", log_id(n->cell));
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@ -356,7 +356,7 @@ struct AlumaccWorker
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log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
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n->macc.optimize(SIZE(n->y));
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n->macc.optimize(GetSize(n->y));
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n->macc.to_cell(cell);
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cell->setPort("\\Y", n->y);
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cell->fixup_parameters();
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@ -391,7 +391,7 @@ struct AlumaccWorker
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RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
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RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
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if (B < A && SIZE(B)) {
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if (B < A && GetSize(B)) {
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cmp_less = !cmp_less;
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std::swap(A, B);
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}
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@ -409,7 +409,7 @@ struct AlumaccWorker
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n->a = A;
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n->b = B;
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n->c = RTLIL::S1;
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n->y = module->addWire(NEW_ID, std::max(SIZE(A), SIZE(B)));
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n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
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n->is_signed = is_signed;
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n->invert_b = true;
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sig_alu[RTLIL::SigSig(A, B)].insert(n);
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@ -431,7 +431,7 @@ struct AlumaccWorker
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RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
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RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
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if (B < A && SIZE(B))
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if (B < A && GetSize(B))
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std::swap(A, B);
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alunode_t *n = nullptr;
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@ -455,12 +455,12 @@ struct AlumaccWorker
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for (auto &it1 : sig_alu)
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for (auto n : it1.second)
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{
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if (SIZE(n->b) == 0 && SIZE(n->c) == 0 && SIZE(n->cmp) == 0)
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if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
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{
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n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
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log(" creating $pos cell for ");
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for (int i = 0; i < SIZE(n->cells); i++)
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for (int i = 0; i < GetSize(n->cells); i++)
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log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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log(": %s\n", log_id(n->alu_cell));
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@ -471,17 +471,17 @@ struct AlumaccWorker
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alu_counter++;
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log(" creating $alu cell for ");
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for (int i = 0; i < SIZE(n->cells); i++)
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for (int i = 0; i < GetSize(n->cells); i++)
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log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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log(": %s\n", log_id(n->alu_cell));
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n->alu_cell->setPort("\\A", n->a);
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n->alu_cell->setPort("\\B", n->b);
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n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0);
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n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
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n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
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n->alu_cell->setPort("\\Y", n->y);
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n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
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n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
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n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
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n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));
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n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
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for (auto &it : n->cmp)
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@ -498,10 +498,10 @@ struct AlumaccWorker
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if (cmp_eq) sig.append(n->get_eq());
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if (cmp_ne) sig.append(n->get_ne());
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if (SIZE(sig) > 1)
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if (GetSize(sig) > 1)
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sig = module->ReduceOr(NEW_ID, sig);
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sig.extend(SIZE(cmp_y));
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sig.extend(GetSize(cmp_y));
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module->connect(cmp_y, sig);
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}
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