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Renamed SIZE() to GetSize() because of name collision on Win32

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This commit is contained in:
Clifford Wolf 2014-10-10 16:59:44 +02:00
parent c7f5aab625
commit 4569a747f8
48 changed files with 447 additions and 447 deletions
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84
passes/techmap/alumacc.cc
View file

@ -48,51 +48,51 @@ struct AlumaccWorker
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
if (SIZE(cached_lt) == 0)
if (GetSize(cached_lt) == 0)
cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
return cached_lt;
}
RTLIL::SigSpec get_gt() {
if (SIZE(cached_gt) == 0)
if (GetSize(cached_gt) == 0)
cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
return cached_gt;
}
RTLIL::SigSpec get_eq() {
if (SIZE(cached_eq) == 0)
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (SIZE(cached_ne) == 0)
if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
return cached_ne;
}
RTLIL::SigSpec get_cf() {
if (SIZE(cached_cf) == 0) {
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort("\\CO");
log_assert(SIZE(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[SIZE(cached_cf)-1]);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
}
return cached_cf;
}
RTLIL::SigSpec get_of() {
if (SIZE(cached_of) == 0) {
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")};
log_assert(SIZE(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[SIZE(cached_of)-1], cached_of[SIZE(cached_of)-2]);
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
return cached_of;
}
RTLIL::SigSpec get_sf() {
if (SIZE(cached_sf) == 0) {
if (GetSize(cached_sf) == 0) {
cached_sf = alu_cell->getPort("\\Y");
cached_sf = cached_sf[SIZE(cached_sf)-1];
cached_sf = cached_sf[GetSize(cached_sf)-1];
}
return cached_sf;
}
@ -184,10 +184,10 @@ struct AlumaccWorker
return true;
if (!port.is_signed && port.do_subtract)
return true;
if (SIZE(port.in_b))
port_sizes.push_back(SIZE(port.in_a) + SIZE(port.in_b));
if (GetSize(port.in_b))
port_sizes.push_back(GetSize(port.in_a) + GetSize(port.in_b));
else
port_sizes.push_back(SIZE(port.in_a));
port_sizes.push_back(GetSize(port.in_a));
}
std::sort(port_sizes.begin(), port_sizes.end());
@ -224,11 +224,11 @@ struct AlumaccWorker
if (delete_nodes.count(n))
continue;
for (int i = 0; i < SIZE(n->macc.ports); i++)
for (int i = 0; i < GetSize(n->macc.ports); i++)
{
auto &port = n->macc.ports[i];
if (SIZE(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
continue;
auto other_n = sig_macc.at(port.in_a);
@ -236,13 +236,13 @@ struct AlumaccWorker
if (other_n->users > 1)
continue;
if (SIZE(other_n->y) != SIZE(n->y) && macc_may_overflow(other_n->macc, SIZE(other_n->y), port.is_signed))
if (GetSize(other_n->y) != GetSize(n->y) && macc_may_overflow(other_n->macc, GetSize(other_n->y), port.is_signed))
continue;
log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell));
bool do_subtract = port.do_subtract;
for (int j = 0; j < SIZE(other_n->macc.ports); j++) {
for (int j = 0; j < GetSize(other_n->macc.ports); j++) {
if (do_subtract)
other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract;
if (j == 0)
@ -278,38 +278,38 @@ struct AlumaccWorker
alunode_t *alunode;
for (auto &port : n->macc.ports)
if (SIZE(port.in_b) > 0) {
if (GetSize(port.in_b) > 0) {
goto next_macc;
} else if (SIZE(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
} else if (GetSize(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
C.append(port.in_a);
} else if (SIZE(A) || port.do_subtract) {
if (SIZE(B))
} else if (GetSize(A) || port.do_subtract) {
if (GetSize(B))
goto next_macc;
B = port.in_a;
b_signed = port.is_signed;
subtract_b = port.do_subtract;
} else {
if (SIZE(A))
if (GetSize(A))
goto next_macc;
A = port.in_a;
a_signed = port.is_signed;
}
if (!a_signed || !b_signed) {
if (SIZE(A) == SIZE(n->y))
if (GetSize(A) == GetSize(n->y))
a_signed = false;
if (SIZE(B) == SIZE(n->y))
if (GetSize(B) == GetSize(n->y))
b_signed = false;
if (a_signed != b_signed)
goto next_macc;
}
if (SIZE(A) == 0 && SIZE(C) > 0) {
if (GetSize(A) == 0 && GetSize(C) > 0) {
A = C[0];
C.remove(0);
}
if (SIZE(B) == 0 && SIZE(C) > 0) {
if (GetSize(B) == 0 && GetSize(C) > 0) {
B = C[0];
C.remove(0);
}
@ -317,10 +317,10 @@ struct AlumaccWorker
if (subtract_b)
C.append(RTLIL::S1);
if (SIZE(C) > 1)
if (GetSize(C) > 1)
goto next_macc;
if (!subtract_b && B < A && SIZE(B))
if (!subtract_b && B < A && GetSize(B))
std::swap(A, B);
log(" creating $alu model for $macc %s.\n", log_id(n->cell));
@ -356,7 +356,7 @@ struct AlumaccWorker
log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
n->macc.optimize(SIZE(n->y));
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
cell->setPort("\\Y", n->y);
cell->fixup_parameters();
@ -391,7 +391,7 @@ struct AlumaccWorker
RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
if (B < A && SIZE(B)) {
if (B < A && GetSize(B)) {
cmp_less = !cmp_less;
std::swap(A, B);
}
@ -409,7 +409,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = RTLIL::S1;
n->y = module->addWire(NEW_ID, std::max(SIZE(A), SIZE(B)));
n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
@ -431,7 +431,7 @@ struct AlumaccWorker
RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
if (B < A && SIZE(B))
if (B < A && GetSize(B))
std::swap(A, B);
alunode_t *n = nullptr;
@ -455,12 +455,12 @@ struct AlumaccWorker
for (auto &it1 : sig_alu)
for (auto n : it1.second)
{
if (SIZE(n->b) == 0 && SIZE(n->c) == 0 && SIZE(n->cmp) == 0)
if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
log(" creating $pos cell for ");
for (int i = 0; i < SIZE(n->cells); i++)
for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
@ -471,17 +471,17 @@ struct AlumaccWorker
alu_counter++;
log(" creating $alu cell for ");
for (int i = 0; i < SIZE(n->cells); i++)
for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b);
n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
n->alu_cell->setPort("\\Y", n->y);
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
@ -498,10 +498,10 @@ struct AlumaccWorker
if (cmp_eq) sig.append(n->get_eq());
if (cmp_ne) sig.append(n->get_ne());
if (SIZE(sig) > 1)
if (GetSize(sig) > 1)
sig = module->ReduceOr(NEW_ID, sig);
sig.extend(SIZE(cmp_y));
sig.extend(GetSize(cmp_y));
module->connect(cmp_y, sig);
}

2
passes/techmap/dfflibmap.cc
View file

@ -412,7 +412,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, SIZE(old_sig));
sig = module->addWire(NEW_ID, GetSize(old_sig));
module->addNotGate(NEW_ID, sig, old_sig);
} else
if ('a' <= port.second && port.second <= 'z') {

66
passes/techmap/maccmap.cc
View file

@ -62,16 +62,16 @@ struct MaccmapWorker
void add(RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract)
{
if (SIZE(a) < SIZE(b))
if (GetSize(a) < GetSize(b))
std::swap(a, b);
a.extend(width, is_signed);
if (SIZE(b) > width)
if (GetSize(b) > width)
b.extend(width, is_signed);
for (int i = 0; i < SIZE(b); i++)
if (is_signed && i+1 == SIZE(b))
for (int i = 0; i < GetSize(b); i++)
if (is_signed && i+1 == GetSize(b))
{
a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
@ -86,7 +86,7 @@ struct MaccmapWorker
void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2)
{
int start_index = 0, stop_index = SIZE(in1);
int start_index = 0, stop_index = GetSize(in1);
while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
start_index++;
@ -96,18 +96,18 @@ struct MaccmapWorker
if (start_index == stop_index)
{
out1 = RTLIL::SigSpec(0, SIZE(in1));
out2 = RTLIL::SigSpec(0, SIZE(in1));
out1 = RTLIL::SigSpec(0, GetSize(in1));
out2 = RTLIL::SigSpec(0, GetSize(in1));
}
else
{
RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, SIZE(in1)-stop_index);
RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, GetSize(in1)-stop_index);
in1 = in1.extract(start_index, stop_index-start_index);
in2 = in2.extract(start_index, stop_index-start_index);
in3 = in3.extract(start_index, stop_index-start_index);
int width = SIZE(in1);
int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
@ -165,12 +165,12 @@ struct MaccmapWorker
while (1)
{
int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits);
int free_bit_slots = tree_bit_slots(GetSize(summands)) - GetSize(tree_sum_bits);
int max_depth = 0, max_position = 0;
for (int i = 0; i < width; i++)
if (max_depth <= SIZE(bits.at(i))) {
max_depth = SIZE(bits.at(i));
if (max_depth <= GetSize(bits.at(i))) {
max_depth = GetSize(bits.at(i));
max_position = i;
}
@ -179,14 +179,14 @@ struct MaccmapWorker
int required_bits = 0;
for (int i = 0; i <= max_position; i++)
if (SIZE(bits.at(i)) == max_depth)
if (GetSize(bits.at(i)) == max_depth)
required_bits += 1 << i;
if (required_bits > free_bit_slots)
break;
for (int i = 0; i <= max_position; i++)
if (SIZE(bits.at(i)) == max_depth) {
if (GetSize(bits.at(i)) == max_depth) {
auto it = bits.at(i).begin();
RTLIL::SigBit bit = *it;
for (int k = 0; k < (1 << i); k++, free_bit_slots--)
@ -200,23 +200,23 @@ struct MaccmapWorker
}
if (!tree_sum_bits.empty())
log(" packed %d (%d) bits / %d words into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits, count_tree_words);
log(" packed %d (%d) bits / %d words into adder tree\n", GetSize(tree_sum_bits), unique_tree_bits, count_tree_words);
if (SIZE(summands) == 0) {
if (GetSize(summands) == 0) {
log_assert(tree_sum_bits.empty());
return RTLIL::SigSpec(0, width);
}
if (SIZE(summands) == 1) {
if (GetSize(summands) == 1) {
log_assert(tree_sum_bits.empty());
return summands.front();
}
while (SIZE(summands) > 2)
while (GetSize(summands) > 2)
{
std::vector<RTLIL::SigSpec> new_summands;
for (int i = 0; i < SIZE(summands); i += 3)
if (i+2 < SIZE(summands)) {
for (int i = 0; i < GetSize(summands); i += 3)
if (i+2 < GetSize(summands)) {
RTLIL::SigSpec in1 = summands[i];
RTLIL::SigSpec in2 = summands[i+1];
RTLIL::SigSpec in3 = summands[i+2];
@ -264,7 +264,7 @@ extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{
int width = SIZE(cell->getPort("\\Y"));
int width = GetSize(cell->getPort("\\Y"));
Macc macc;
macc.from_cell(cell);
@ -279,15 +279,15 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
for (auto &port : macc.ports)
if (SIZE(port.in_b) == 0)
if (GetSize(port.in_b) == 0)
log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a),
SIZE(port.in_a), port.is_signed ? "signed" : "unsigned");
GetSize(port.in_a), port.is_signed ? "signed" : "unsigned");
else
log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b),
SIZE(port.in_a), SIZE(port.in_b), port.is_signed ? "signed" : "unsigned");
GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned");
if (SIZE(macc.bit_ports) != 0)
log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), SIZE(macc.bit_ports));
if (GetSize(macc.bit_ports) != 0)
log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), GetSize(macc.bit_ports));
if (unmap)
{
@ -296,10 +296,10 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &port : macc.ports) {
summand_t this_summand;
if (SIZE(port.in_b)) {
if (GetSize(port.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed);
} else if (SIZE(port.in_a) != width) {
} else if (GetSize(port.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed);
} else {
@ -312,14 +312,14 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &bit : macc.bit_ports)
summands.push_back(summand_t(bit, false));
if (SIZE(summands) == 0)
if (GetSize(summands) == 0)
summands.push_back(summand_t(RTLIL::SigSpec(0, width), false));
while (SIZE(summands) > 1)
while (GetSize(summands) > 1)
{
std::vector<summand_t> new_summands;
for (int i = 0; i < SIZE(summands); i += 2) {
if (i+1 < SIZE(summands)) {
for (int i = 0; i < GetSize(summands); i += 2) {
if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.second = summands[i].second && summands[i+1].second;
@ -348,7 +348,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
MaccmapWorker worker(module, width);
for (auto &port : macc.ports)
if (SIZE(port.in_b) == 0)
if (GetSize(port.in_b) == 0)
worker.add(port.in_a, port.is_signed, port.do_subtract);
else
worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract);

18
passes/techmap/simplemap.cc
View file

@ -32,9 +32,9 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < SIZE(sig_y); i++) {
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\Y", sig_y[i]);
@ -46,7 +46,7 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
@ -57,14 +57,14 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
if (cell->type == "$xnor")
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
for (int i = 0; i < SIZE(sig_y); i++) {
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_t[i]);
gate->setPort("\\Y", sig_y[i]);
@ -80,7 +80,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$xnor") gate_type = "$_XOR_";
log_assert(!gate_type.empty());
for (int i = 0; i < SIZE(sig_y); i++) {
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
@ -238,7 +238,7 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
for (int i = 0; i < SIZE(sig_y); i++) {
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);

10
passes/techmap/techmap.cc
View file

@ -97,7 +97,7 @@ struct TechmapWorker
std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
for (auto conn : cell->connections())
for (int i = 0; i < SIZE(conn.second); i++) {
for (int i = 0; i < GetSize(conn.second); i++) {
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
if (verbose)
@ -162,7 +162,7 @@ struct TechmapWorker
log(" %s",RTLIL::id2cstr(it.first));
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
log_assert(SIZE(tpl->processes) == 0);
log_assert(GetSize(tpl->processes) == 0);
} else
log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
}
@ -303,7 +303,7 @@ struct TechmapWorker
RTLIL::SigSpec sig = sigmap(conn.second);
sig.remove_const();
if (SIZE(sig) == 0)
if (GetSize(sig) == 0)
continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) {
@ -383,7 +383,7 @@ struct TechmapWorker
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, SIZE(c.second));
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name == "\\Y" || w->name == "\\Q")
w->port_output = true;
else
@ -630,7 +630,7 @@ struct TechmapWorker
}
for (auto conn : cell->connections())
for (int i = 0; i < SIZE(conn.second); i++)
for (int i = 0; i < GetSize(conn.second); i++)
{
RTLIL::SigBit bit = sigmap(conn.second[i]);
RTLIL::SigBit tplbit(tpl->wire(conn.first), i);