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https://github.com/YosysHQ/yosys
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Renamed SIZE() to GetSize() because of name collision on Win32
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parent
c7f5aab625
commit
4569a747f8
48 changed files with 447 additions and 447 deletions
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@ -73,9 +73,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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sig_aa.replace(sig_y, sig_a);
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RTLIL::SigSpec sig_bb;
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for (int i = 0; i < SIZE(sig_b)/SIZE(sig_a); i++) {
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for (int i = 0; i < GetSize(sig_b)/GetSize(sig_a); i++) {
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RTLIL::SigSpec s = sig;
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s.replace(sig_y, sig_b.extract(i*SIZE(sig_a), SIZE(sig_a)));
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s.replace(sig_y, sig_b.extract(i*GetSize(sig_a), GetSize(sig_a)));
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sig_bb.append(s);
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}
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@ -98,8 +98,8 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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if (!find_states(sig_aa, dff_out, ctrl, states))
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return false;
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for (int i = 0; i < SIZE(sig_bb)/SIZE(sig_aa); i++) {
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if (!find_states(sig_bb.extract(i*SIZE(sig_aa), SIZE(sig_aa)), dff_out, ctrl, states))
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for (int i = 0; i < GetSize(sig_bb)/GetSize(sig_aa); i++) {
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if (!find_states(sig_bb.extract(i*GetSize(sig_aa), GetSize(sig_aa)), dff_out, ctrl, states))
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return false;
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}
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}
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@ -110,7 +110,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
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{
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if (dont_care.size() > 0) {
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for (int i = 0; i < SIZE(sig); i++)
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for (int i = 0; i < GetSize(sig); i++)
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if (dont_care.extract(sig[i]).size() > 0)
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sig[i] = noconst_state;
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}
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@ -118,7 +118,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
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ce.assign_map.apply(sig);
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ce.values_map.apply(sig);
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for (int i = 0; i < SIZE(sig); i++)
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for (int i = 0; i < GetSize(sig); i++)
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if (sig[i].wire != NULL)
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sig[i] = noconst_state;
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@ -148,7 +148,7 @@ undef_bit_in_next_state:
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tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx);
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std::map<RTLIL::SigBit, int> ctrl_in_bit_indices;
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for (int i = 0; i < SIZE(ctrl_in); i++)
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for (int i = 0; i < GetSize(ctrl_in); i++)
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ctrl_in_bit_indices[ctrl_in[i]] = i;
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for (auto &it : ctrl_in_bit_indices)
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@ -290,7 +290,7 @@ static void extract_fsm(RTLIL::Wire *wire)
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log(" fsm extraction failed: state selection tree is not closed.\n");
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return;
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}
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if (SIZE(states) <= 1) {
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if (GetSize(states) <= 1) {
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log(" fsm extraction failed: at least two states are required.\n");
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return;
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}
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