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https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
Renamed SIZE() to GetSize() because of name collision on Win32
This commit is contained in:
Clifford Wolf
parent
c7f5aab625
commit
4569a747f8
48 changed files with 447 additions and 447 deletions
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@ -941,10 +941,10 @@ void RTLIL::Module::check()
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for (auto &it2 : it.second->attributes)
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log_assert(!it2.first.empty());
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if (it.second->port_id) {
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log_assert(SIZE(ports) >= it.second->port_id);
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log_assert(GetSize(ports) >= it.second->port_id);
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log_assert(ports.at(it.second->port_id-1) == it.first);
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log_assert(it.second->port_input || it.second->port_output);
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if (SIZE(ports_declared) < it.second->port_id)
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if (GetSize(ports_declared) < it.second->port_id)
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ports_declared.resize(it.second->port_id);
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log_assert(ports_declared[it.second->port_id-1] == false);
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ports_declared[it.second->port_id-1] = true;
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@ -953,7 +953,7 @@ void RTLIL::Module::check()
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}
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for (auto port_declared : ports_declared)
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log_assert(port_declared == true);
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log_assert(SIZE(ports) == SIZE(ports_declared));
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log_assert(GetSize(ports) == GetSize(ports_declared));
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for (auto &it : memories) {
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log_assert(it.first == it.second->name);
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@ -1811,25 +1811,25 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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return;
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if (type == "$mux" || type == "$pmux") {
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parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
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parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
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if (type == "$pmux")
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parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
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parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
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check();
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return;
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}
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if (type == "$lut") {
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parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
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parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
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return;
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}
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if (type == "$fa") {
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parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
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parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
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return;
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}
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if (type == "$lcu") {
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parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
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parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
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return;
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}
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@ -1842,7 +1842,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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else if (parameters.count("\\A_SIGNED") == 0)
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parameters["\\A_SIGNED"] = false;
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}
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parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
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parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
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}
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if (connections_.count("\\B")) {
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@ -1852,11 +1852,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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else if (parameters.count("\\B_SIGNED") == 0)
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parameters["\\B_SIGNED"] = false;
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}
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parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
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parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
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}
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if (connections_.count("\\Y"))
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parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
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parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
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check();
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}
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@ -1872,7 +1872,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
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{
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wire = NULL;
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data = value.bits;
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width = SIZE(data);
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width = GetSize(data);
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offset = 0;
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}
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@ -1896,7 +1896,7 @@ RTLIL::SigChunk::SigChunk(const std::string &str)
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{
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wire = NULL;
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data = RTLIL::Const(str).bits;
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width = SIZE(data);
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width = GetSize(data);
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offset = 0;
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}
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@ -1904,7 +1904,7 @@ RTLIL::SigChunk::SigChunk(int val, int width)
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{
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wire = NULL;
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data = RTLIL::Const(val, width).bits;
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this->width = SIZE(data);
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this->width = GetSize(data);
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offset = 0;
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}
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@ -1912,7 +1912,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
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{
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wire = NULL;
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data = RTLIL::Const(bit, width).bits;
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this->width = SIZE(data);
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this->width = GetSize(data);
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offset = 0;
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}
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@ -2258,7 +2258,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
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for (int i = 0; i < SIZE(pattern.bits_); i++)
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for (int i = 0; i < GetSize(pattern.bits_); i++)
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if (pattern.bits_[i].wire != NULL)
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rules[pattern.bits_[i]] = with.bits_[i];
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@ -2280,7 +2280,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
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unpack();
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other->unpack();
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for (int i = 0; i < SIZE(bits_); i++) {
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for (int i = 0; i < GetSize(bits_); i++) {
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auto it = rules.find(bits_[i]);
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if (it != rules.end())
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other->bits_[i] = it->second;
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@ -2333,12 +2333,12 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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std::vector<RTLIL::SigBit> new_bits, new_other_bits;
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new_bits.resize(SIZE(bits_));
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new_bits.resize(GetSize(bits_));
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if (other != NULL)
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new_other_bits.resize(SIZE(bits_));
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new_other_bits.resize(GetSize(bits_));
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int k = 0;
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for (int i = 0; i < SIZE(bits_); i++) {
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for (int i = 0; i < GetSize(bits_); i++) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i]))
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continue;
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if (other != NULL)
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@ -2351,11 +2351,11 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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new_other_bits.resize(k);
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bits_.swap(new_bits);
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width_ = SIZE(bits_);
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width_ = GetSize(bits_);
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if (other != NULL) {
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other->bits_.swap(new_other_bits);
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other->width_ = SIZE(other->bits_);
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other->width_ = GetSize(other->bits_);
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}
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check();
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@ -2418,7 +2418,7 @@ void RTLIL::SigSpec::remove_const()
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cover("kernel.rtlil.sigspec.remove_const.packed");
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std::vector<RTLIL::SigChunk> new_chunks;
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new_chunks.reserve(SIZE(chunks_));
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new_chunks.reserve(GetSize(chunks_));
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width_ = 0;
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for (auto &chunk : chunks_)
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@ -2624,7 +2624,7 @@ void RTLIL::SigSpec::check() const
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{
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cover("kernel.rtlil.sigspec.check.unpacked");
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log_assert(width_ == SIZE(bits_));
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log_assert(width_ == GetSize(bits_));
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log_assert(chunks_.empty());
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}
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}
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@ -2699,7 +2699,7 @@ bool RTLIL::SigSpec::is_wire() const
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cover("kernel.rtlil.sigspec.is_wire");
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pack();
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return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
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return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
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}
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bool RTLIL::SigSpec::is_chunk() const
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@ -2707,7 +2707,7 @@ bool RTLIL::SigSpec::is_chunk() const
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cover("kernel.rtlil.sigspec.is_chunk");
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pack();
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return SIZE(chunks_) == 1;
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return GetSize(chunks_) == 1;
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}
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bool RTLIL::SigSpec::is_fully_const() const
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@ -2770,7 +2770,7 @@ bool RTLIL::SigSpec::as_bool() const
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cover("kernel.rtlil.sigspec.as_bool");
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pack();
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log_assert(is_fully_const() && SIZE(chunks_) <= 1);
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log_assert(is_fully_const() && GetSize(chunks_) <= 1);
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if (width_)
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return RTLIL::Const(chunks_[0].data).as_bool();
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return false;
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@ -2781,7 +2781,7 @@ int RTLIL::SigSpec::as_int(bool is_signed) const
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cover("kernel.rtlil.sigspec.as_int");
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pack();
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log_assert(is_fully_const() && SIZE(chunks_) <= 1);
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log_assert(is_fully_const() && GetSize(chunks_) <= 1);
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if (width_)
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return RTLIL::Const(chunks_[0].data).as_int(is_signed);
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return 0;
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@ -2809,7 +2809,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
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cover("kernel.rtlil.sigspec.as_const");
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pack();
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log_assert(is_fully_const() && SIZE(chunks_) <= 1);
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log_assert(is_fully_const() && GetSize(chunks_) <= 1);
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if (width_)
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return chunks_[0].data;
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return RTLIL::Const();
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