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add tests

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N. Engelhardt 2025-10-14 15:48:16 +02:00
parent 1f11b2c529
commit 4513783a02
4 changed files with 38 additions and 0 deletions
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13
tests/verific/ext_ramnet_err.sv Normal file
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module sub_rom (input clk, input [3:0] addr, output reg [7:0] data);
reg [7:0] mem [0:15];
always @(posedge clk)
data <= mem[addr];
endmodule
module top (input clk, input [3:0] addr, output [7:0] data, input [3:0] f_addr, input [7:0] f_data);
sub_rom u_sub_rom (clk, addr, data);
always @(posedge clk)
assume(u_sub_rom.mem[f_addr] == f_data);
endmodule