mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-15 08:44:11 +00:00
rtlil: forbid rewrite_sigspecs in signorm
This commit is contained in:
parent
d39ce10601
commit
44917f50d9
1 changed files with 2 additions and 0 deletions
|
|
@ -2359,6 +2359,7 @@ inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
|
|||
template<typename T>
|
||||
void RTLIL::Module::rewrite_sigspecs(T &functor)
|
||||
{
|
||||
log_assert(sig_norm_index == nullptr);
|
||||
for (auto &it : cells_)
|
||||
it.second->rewrite_sigspecs(functor);
|
||||
for (auto &it : processes)
|
||||
|
|
@ -2372,6 +2373,7 @@ void RTLIL::Module::rewrite_sigspecs(T &functor)
|
|||
template<typename T>
|
||||
void RTLIL::Module::rewrite_sigspecs2(T &functor)
|
||||
{
|
||||
log_assert(sig_norm_index == nullptr);
|
||||
for (auto &it : cells_)
|
||||
it.second->rewrite_sigspecs2(functor);
|
||||
for (auto &it : processes)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue