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	"abc_padding" attr for blackbox outputs that were padded, remove them later
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					 2 changed files with 22 additions and 4 deletions
				
			
		|  | @ -350,6 +350,8 @@ struct XAigerWriter | |||
| 				if (!box_module || !box_module->attributes.count("\\abc_box_id")) | ||||
| 					continue; | ||||
| 
 | ||||
| 				bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); | ||||
| 
 | ||||
| 				// Fully pad all unused input connections of this box cell with S0
 | ||||
| 				// Fully pad all undriven output connections of this box cell with anonymous wires
 | ||||
| 				// NB: Assume box_module->ports are sorted alphabetically
 | ||||
|  | @ -394,7 +396,10 @@ struct XAigerWriter | |||
| 							rhs = it->second; | ||||
| 						} | ||||
| 						else { | ||||
| 							rhs = module->addWire(NEW_ID, GetSize(w)); | ||||
| 							Wire *wire = module->addWire(NEW_ID, GetSize(w)); | ||||
| 							if (blackbox) | ||||
| 								wire->set_bool_attribute(ID(abc_padding)); | ||||
| 							rhs = wire; | ||||
| 							cell->setPort(port_name, rhs); | ||||
| 						} | ||||
| 
 | ||||
|  |  | |||
|  | @ -606,7 +606,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 				existing_cell = module->cell(c->name); | ||||
| 				log_assert(existing_cell); | ||||
| 				cell = module->addCell(remap_name(c->name), c->type); | ||||
| 				module->swap_names(cell, existing_cell); | ||||
| 			} | ||||
| 
 | ||||
| 			if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; | ||||
|  | @ -642,8 +641,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | |||
| 			} | ||||
| 		} | ||||
| 
 | ||||
| 		for (auto cell : boxes) | ||||
| 			module->remove(cell); | ||||
| 		for (auto existing_cell : boxes) { | ||||
| 			Cell *cell = module->cell(remap_name(existing_cell->name)); | ||||
| 			if (cell) { | ||||
| 				for (auto &conn : existing_cell->connections()) { | ||||
| 					if (!conn.second.is_wire()) | ||||
| 						continue; | ||||
| 					Wire *wire = conn.second.as_wire(); | ||||
| 					if (!wire->get_bool_attribute(ID(abc_padding))) | ||||
| 						continue; | ||||
| 					cell->unsetPort(conn.first); | ||||
| 					log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second)); | ||||
| 				} | ||||
| 				module->swap_names(cell, existing_cell); | ||||
| 			} | ||||
| 			module->remove(existing_cell); | ||||
| 		} | ||||
| 
 | ||||
| 		// Copy connections (and rename) from mapped_mod to module
 | ||||
| 		for (auto conn : mapped_mod->connections()) { | ||||
|  |  | |||
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