diff --git a/flake.nix b/flake.nix index 404f29dc4..8ab16989a 100644 --- a/flake.nix +++ b/flake.nix @@ -14,11 +14,11 @@ }; # TODO: don't override src when ./abc is empty # which happens when the command used is `nix build` and not `nix build ?submodules=1` - abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;}); + abc-verifier = pkgs.abc-verifier; yosys = pkgs.llvmPackages.libcxxStdenv.mkDerivation { name = "yosys"; src = ./. ; - buildInputs = with pkgs; [ bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream tracy ]; + buildInputs = with pkgs; [ stdenv.cc.cc bison flex libffi tcl readline python3 zlib git pkg-configUpstream tracy ]; checkInputs = with pkgs; [ gtest ]; propagatedBuildInputs = [ abc-verifier ]; preConfigure = "make config-clang"; @@ -42,7 +42,7 @@ packages.default = yosys; defaultPackage = yosys; devShell = pkgs.mkShell { - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier tracy ]; + buildInputs = with pkgs; [ stdenv.cc.cc bison flex libffi tcl readline python3 zlib git gtest abc-verifier tracy ]; }; } ); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 65b675184..ef2df5719 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -28,6 +28,7 @@ #include #include #include +#include YOSYS_NAMESPACE_BEGIN @@ -2424,6 +2425,20 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth return wire; } +template +void scream(AAAA* aaa) { + unsigned char *ptr = reinterpret_cast(aaa); + for (size_t i = 0; i < sizeof(AAAA); ++i) { + std::cout << std::hex << std::setw(2) << std::setfill('0') << static_cast(ptr[i]) << ' '; + } + std::cout << std::endl; +} +template +void scream(const char* ctx, AAAA* aaa) { + log("%s\n", ctx); + scream(aaa); +} + RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) { RTLIL::Cell *cell = new RTLIL::Cell; @@ -2431,6 +2446,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) log("ptr 0x%016X\n", cell); cell->name = name; cell->type = type; + scream("addCell pre", cell); if (RTLIL::Cell::is_legacy_type(type)) { cell->legacy = new RTLIL::OldCell; cell->legacy->name = name; @@ -2448,6 +2464,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) new (&conn.second) SigSpec(); } } + scream("addCell post", cell); add(cell); return cell; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 986cc0962..1cf86e9fe 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1614,7 +1614,7 @@ public: }; -// $not +// $not etc struct RTLIL::Unary { SigSpec a; SigSpec y; @@ -1662,7 +1662,6 @@ public: RTLIL::IdString type; RTLIL::IdString name; // TODO delete? RTLIL::Module* module; // TODO delete - bool has_attrs; union { RTLIL::Unary not_; RTLIL::Unary pos; @@ -1869,8 +1868,8 @@ public: typedef std::input_iterator_tag iterator_category; typedef std::pair value_type; typedef ptrdiff_t difference_type; - typedef std::pair pointer; - typedef std::pair reference; + typedef std::pair pointer; + typedef std::pair reference; Cell* parent; int position; public: @@ -1885,7 +1884,7 @@ public: bool operator!=(const const_iterator &other) const { return !(*this == other); } - const std::pair operator*() const { + const std::pair operator*() const { if (parent->is_legacy()) { auto it = parent->legacy->parameters.begin(); it += position; @@ -1902,8 +1901,8 @@ public: throw std::out_of_range("FakeParams::const_iterator::operator*() const"); } } - std::pair operator->() { return operator*(); } - const std::pair operator->() const { return operator*(); } + // std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } }; const_iterator begin() const { return const_iterator(parent, 0); @@ -2116,8 +2115,8 @@ public: typedef std::input_iterator_tag iterator_category; typedef std::pair value_type; typedef ptrdiff_t difference_type; - typedef std::pair pointer; - typedef std::pair reference; + typedef std::pair pointer; + typedef std::pair reference; Cell* parent; int position; public: @@ -2132,7 +2131,7 @@ public: bool operator!=(const const_iterator &other) const { return !(*this == other); } - const std::pair operator*() const { + const std::pair operator*() const { if (parent->is_legacy()) { auto it = parent->legacy->connections_.begin(); it += position; @@ -2149,8 +2148,8 @@ public: throw std::out_of_range("FakeConns::const_iterator::operator*() const"); } } - std::pair operator->() { return operator*(); } - const std::pair operator->() const { return operator*(); } + // std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } }; const_iterator begin() const { return const_iterator(parent, 0); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 79eb6b6ea..ff7204f29 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -41,6 +41,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, { RTLIL::Module *module = design->addModule(ID(gold)); RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type); + for (auto para : cell->parameters) + log("param %s is %s\n", para.first.c_str(), para.second.as_string().c_str()); + // for (auto para : cell->connections) + // log("param %s is %s\n", para.first.c_str(), para.second.as_string()); RTLIL::Wire *wire; if (cell_type.in(ID($mux), ID($pmux)))