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Added Xilinx bram black-box modules

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This commit is contained in:
Clifford Wolf 2015-04-06 08:44:30 +02:00
parent c0e2b3eb11
commit 4389d9306e
3 changed files with 322 additions and 0 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -69,6 +69,7 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" begin:\n");
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" read_verilog -lib +/xilinx/brams_bb.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@ -158,6 +159,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "begin"))
{
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
}