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Add (* gclk *) attribute support

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-06-01 13:25:42 +02:00
parent f273291dfe
commit 4372cf690d
4 changed files with 23 additions and 1 deletions
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README.md
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@ -418,7 +418,9 @@ Non-standard or SystemVerilog features for formal verification
supported in any clocked block.
- The syntax ``@($global_clock)`` can be used to create FFs that have no
explicit clock input ($ff cells).
explicit clock input ($ff cells). The same can be achieved by using
``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
is marked with the ``(* gclk *)`` Verilog attribute.
Supported features from SystemVerilog