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Addressed review comments

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This commit is contained in:
Miodrag Milanovic 2019-12-21 20:23:23 +01:00
parent 1937091f62
commit 436fea9e69
2 changed files with 3 additions and 3 deletions
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tests/arch/xilinx/tribuf.ys
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@ -7,7 +7,6 @@ synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
select -assert-count 2 t:IBUF
select -assert-count 1 t:INV
select -assert-count 1 t:OBUFT