3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-10 08:03:26 +00:00

Refactor code to avoid code duplication + added comments

This commit is contained in:
Ruben Undheim 2018-10-20 12:45:51 +02:00
parent 397dfccb30
commit 436e3c0a7c
4 changed files with 113 additions and 136 deletions

View file

@ -308,6 +308,11 @@ namespace AST
// call a DPI function
AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);
// Helper functions related to handling SystemVerilog interfaces
std::pair<std::string,std::string> split_modport_from_type(std::string name_type);
AstNode * find_modport(AstNode *intf, std::string name);
void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
}
namespace AST_INTERNAL