mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

code split and cleanup

Browse source
This commit is contained in:
Miodrag Milanovic 2024-03-19 09:15:04 +01:00
parent 9eebc80170
commit 4367e176fb
1 changed files with 141 additions and 90 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

183
frontends/verific/verific.cc
View file

@ -230,69 +230,70 @@ RTLIL::Const mkconst_str(const std::string &str)
val.flags |= RTLIL::CONST_FLAG_STRING; val.flags |= RTLIL::CONST_FLAG_STRING;
return val; return val;
} }
// When used as attributes or parameter values Verific constants come already processed.
// - Real string values are already under quotes static const RTLIL::Const extract_vhdl_boolean(std::string &val)
// - Numeric values with specified width are always converted to binary
// - Rest of user defined values are handled as 32bit integers
// - There could be some internal values that are strings without quotes
// so we check if value is all digits or not
//
// Note: For signed values, verific uses <len>'sb<bits> and decimal values can
// also be negative.
static const RTLIL::Const verific_const(const char* type_name, const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
{ {
size_t found; if (val == "false")
return RTLIL::Const::from_string("0");
if (val == "true")
return RTLIL::Const::from_string("1");
log_error("Expecting VHDL boolean value.\n");
}
static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
{
if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
return RTLIL::Const::from_string(val.substr(1,val.size()-2));
log_error("Error parsing VHDL %s.\n", typ.c_str());
}
static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
{
if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
RTLIL::Const c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
if (typ == "signed")
c.flags |= RTLIL::CONST_FLAG_SIGNED;
return c;
}
log_error("Error parsing VHDL %s.\n", typ.c_str());
}
static const RTLIL::Const extract_vhdl_integer(std::string &val)
{
char *end;
return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32);
}
static const RTLIL::Const extract_vhdl_char(std::string &val)
{
if (val.size()==3 && val[0]=='\"' && val.back()=='\"')
return RTLIL::Const((int)val[1], 32);
log_error("Error parsing VHDL character.\n");
}
static const RTLIL::Const extract_real_value(std::string &val)
{
RTLIL::Const c = mkconst_str(val);
c.flags |= RTLIL::CONST_FLAG_REAL;
return c;
}
static const RTLIL::Const extract_vhdl_string(std::string &val)
{
if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
log_error("Error parsing VHDL string.\n");
return RTLIL::Const(val.substr(1,val.size()-2));
}
static const RTLIL::Const extract_vhdl_const(const char *value, bool output_signed)
{
RTLIL::Const c;
char *end; char *end;
int decimal; int decimal;
bool is_signed = false; bool is_signed = false;
RTLIL::Const c;
std::string val = std::string(value); std::string val = std::string(value);
if (obj->IsFromVhdl()) {
if (type_name) {
if (strcmp(type_name, "integer")==0 || strcmp(type_name, "natural")==0 || strcmp(type_name, "positive")==0) {
decimal = std::strtol(value, &end, 10);
c = RTLIL::Const((int)decimal, 32);
} else if (strcmp(type_name, "boolean")==0) {
if (val == "false") {
c = RTLIL::Const::from_string("0");
} else if (val == "true") {
c = RTLIL::Const::from_string("1");
} else
log_error("Error parsing boolean\n");
} else if (strcmp(type_name, "bit")==0 || strcmp(type_name, "STD_LOGIC")==0 || strcmp(type_name, "STD_ULOGIC")==0) {
if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
} else
log_error("Error parsing %s\n", type_name);
} else if (strcmp(type_name, "character")==0) {
if (val.size()>1 && val[0]=='\"' && val.back()=='\"') { if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
c = RTLIL::Const((int)val[1], 32);
} else
log_error("Error parsing character\n");
} else if (strcmp(type_name, "bit_vector")==0 || strcmp(type_name, "STD_LOGIC_VECTOR")==0 || strcmp(type_name, "STD_ULOGIC_VECTOR")==0 ||
strcmp(type_name, "UNSIGNED")==0 || strcmp(type_name, "SIGNED")==0) {
if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
} else
log_error("Error parsing %s\n", type_name);
if (strcmp(type_name, "SIGNED")==0)
is_signed = true;
} else if (strcmp(type_name, "real")==0) {
c = mkconst_str(val);
c.flags |= RTLIL::CONST_FLAG_REAL;
} else if (strcmp(type_name, "string")==0) {
if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
log_error("Error parsing string\n");
c = RTLIL::Const(val.substr(1,val.size()-2));
} else {
if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
c = RTLIL::Const(val.substr(1,val.size()-2));
else if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
c = RTLIL::Const(val.substr(1,val.size()-2));
else
c = RTLIL::Const(val);
}
} else if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
std::string data = val.substr(1,val.size()-2); std::string data = val.substr(1,val.size()-2);
bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; }); bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
if (isBinary) if (isBinary)
@ -311,13 +312,23 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value
c = RTLIL::Const::from_string("1"); c = RTLIL::Const::from_string("1");
} else { } else {
c = mkconst_str(val); c = mkconst_str(val);
log_warning("encoding value '%s' of type '%s' as string found", value, type_name ? type_name : "unknown"); log_warning("encoding value '%s' as string.\n", value);
} }
} else { if (is_signed)
if (type_name && strcmp(type_name, "real")==0) { c.flags |= RTLIL::CONST_FLAG_SIGNED;
c = mkconst_str(val); return c;
c.flags |= RTLIL::CONST_FLAG_REAL; }
} else if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
static const RTLIL::Const extract_verilog_const(const char *value, bool allow_string, bool output_signed)
{
RTLIL::Const c;
char *end;
int decimal;
bool is_signed = false;
size_t found;
std::string val = std::string(value);
if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
c = RTLIL::Const(val.substr(1,val.size()-2)); c = RTLIL::Const(val.substr(1,val.size()-2));
} else if ((found = val.find("'sb")) != std::string::npos) { } else if ((found = val.find("'sb")) != std::string::npos) {
is_signed = output_signed; is_signed = output_signed;
@ -332,15 +343,55 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value
c = RTLIL::Const(val); c = RTLIL::Const(val);
} else { } else {
c = mkconst_str(val); c = mkconst_str(val);
log_warning("encoding value '%s' of type '%s' as string found", value, type_name ? type_name : "unknown"); log_warning("encoding value '%s' as string.\n", value);
} }
}
if (is_signed) if (is_signed)
c.flags |= RTLIL::CONST_FLAG_SIGNED; c.flags |= RTLIL::CONST_FLAG_SIGNED;
return c; return c;
} }
// When used as attributes or parameter values Verific constants come already processed.
// - Real string values are already under quotes
// - Numeric values with specified width are always converted to binary
// - Rest of user defined values are handled as 32bit integers
// - There could be some internal values that are strings without quotes
// so we check if value is all digits or not
//
// Note: For signed values, verific uses <len>'sb<bits> and decimal values can
// also be negative.
static const RTLIL::Const verific_const(const char* type_name, const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
{
std::string val = std::string(value);
// VHDL
if (obj->IsFromVhdl()) {
if (type_name) {
std::string typ = std::string(type_name);
transform(typ.begin(), typ.end(), typ.begin(), ::tolower);
if (typ == "integer" || typ == "natural" || typ=="positive") return extract_vhdl_integer(val);
else if (typ =="boolean") return extract_vhdl_boolean(val);
else if (typ == "bit" || typ =="std_logic" || typ == "std_ulogic") return extract_vhdl_bit(val,typ);
else if (typ == "character") return extract_vhdl_char(val);
else if (typ == "bit_vector" || typ == "std_logic_vector" || typ == "std_ulogic_vector" ||
typ == "unsigned" || typ == "signed") return extract_vhdl_bit_vector(val,typ);
else if (typ == "real") return extract_real_value(val);
else if (typ == "string") return extract_vhdl_string(val);
else {
if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
return RTLIL::Const(val.substr(1,val.size()-2));
else if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
return RTLIL::Const(val.substr(1,val.size()-2));
else
return RTLIL::Const(val);
}
} else extract_vhdl_const(value, output_signed);
}
// SystemVerilog
if (type_name && strcmp(type_name, "real")==0) {
return extract_real_value(val);
} else
return extract_verilog_const(value, allow_string, output_signed);
}
static const std::string verific_unescape(const char *value) static const std::string verific_unescape(const char *value)
{ {
std::string val = std::string(value); std::string val = std::string(value);